Lsi Logic Corporation

Lsi Corporation

Jeffrey M Rogers

Brian A Day

Patrick R Bashford

Christopher McCarty

Stephen M Johnson

Bruce Trunck

Michael R Hede

Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.

Circuit and method to provide configuration of serial ATA queue depth versus number of devices

The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.

Alternate non-volatile memory for robust I/O

The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to provide a first bus-width control signal to select a first bus-width. The circuit also includes a bus controller extension circuit configured to force the first bus-width control signal to a predetermined level when the bus controller is applied to a bus with a second bus controller that is incompatible with the first bus-width. Advantages of the invention include controlling a number of data bits to be transferred between a PCI device and a data bus that does not violate PCI specifications. Other advantages include a programmability of the PCI device to adapt to legacy systems as PCI technology progresses.

Methods and apparatus for signaling to switch between different bus bandwidths

A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to process a message written in the local memory. The circuit may operate independently of the processor. The circuit may be configured to (i) monitor writes to the local memory for the message having a first pointer and (ii) program the DMA engine to copy a first buffer identified by the first pointer in response to the first pointer having a non-null value.

Hardware chain pull

A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal.

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Colorado Springs, CO, United States of America

Jeffrey M Rogers