Xilinx, Inc.

Ionu Security, Inc.

Jeffrey M Mason

David W Bennett

Prasanna Sundararajan

Jay T Young

W Story Leavesley, Iii

Andrew Richard Putnam

Robert Gwilym Dimond

John D Corbett

Bruce E Talley

Arne S Barras

Lauren B Wenzl

Kate L Kelley

Steve E Lass

Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.

Compiler directed cache coherence for many caches generated from high-level language source code

Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.

Processor and cache arrangement with selective caching between first-level and second-level caches

In one embodiment, a system for secure application hosting is provided. The system includes a memory, a first processor coupled to the memory, a second processor coupled to the first processor via a bus, and a data storage device and a network interface coupled to the second processor. The second processor is configured to perform cryptographic processing to provide an encrypted domain, in which the network interface and data storage device operate, and an unencrypted domain, in which the processor and memory operate.

Secure cloud computing infrastructure

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Generation of cache architecture from a high-level language description

Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.

Methods for automatically generating fault mitigation strategies for electronic system designs

A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.

Floating-point processing unit for successive floating-point operations

Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.

Method and apparatus for providing secure intellectual property cores for a programmable logic device

Approaches for sizing first-in-first-out (FIFO) buffers for pipelining functions of a circuit. Functions of the circuit are performed on an input data set, with respective FIFO buffers for buffering data elements between coupled pairs of the functional blocks. While performing the functions of the circuit, a respective current number of elements added to a FIFO buffer since a previous element was removed from the FIFO buffer is counted for each FIFO buffer, and then compared to a respective saved number. The respective current number is saved as a new respective saved number in response to the respective current number being greater than the respective saved number, and the respective current number is reset after the comparing of the respective current number to the respective saved number. Respective sizes for the FIFO buffers are determined as a function of the respective saved numbers and then the sizes are stored.

Determining sizes of FIFO buffers between functional blocks in an electronic circuit

Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.

Versatile bus interface macro for dynamically reconfigurable designs

Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan. Each of the plurality of modules is one of a static module or a reconfigurable module. The one or more logic interface macros include programmable logic of the PLD and are positioned at one or more boundaries between one or more pairs of the plurality of modules. Each of the plurality of modules is implemented using information generated from the capturing step. The modules are assembled using the information generated from the capturing step and implementing step. Routing for a static module can cross a defined implementation area for a reconfigurable module, and a static module can be placed anywhere outside of reconfigurable module areas.

Method and apparatus for modular circuit design for a programmable logic device

Method and apparatus for incremental design is described. More particularly, a text-circuit description of the integrated circuit having logic groups of respective logic instances is obtained. Area groups are created for the logic groups and correspondingly assigned. Unchanged logic groups are guided on an incremental implementation from existing guide files, and changed logic groups are re-implemented in area groups corresponding to the changed logic groups. In this manner, runtime of the unchanged logic groups is reduced by an incremental guide implementation instead of a re-implementation, while performance of such unchanged logic groups is maintained from a prior implementation. Furthermore, degrees of freedom for re-implementing are enhanced for improving a design, as all prior mapping, placing and routing within a changed area group may be stripped for re-implementation.

Incremental design using a group area designation

In modular design flow, logic designers are able to partition a top-level logic design for a PLD into modules and implement any module independently from other modules. Modules are mapped, placed, and routed using selected information derived at the time the top-level logic design is partitioned. Finally, the modules are integrated into the top-level logic design using a guided process. Specifically, the information generated during the partitioning of the top-level design and the implementation of each module is used to guide the implementation of the associated logic in the top-level design. In this manner, the implementation of all modules can proceed in any order or in parallel and the integration of the modules into the top-level design can be done quickly and in any order.

Growing community of inventors

Eldorado Springs, CO, United States of America

Jeffrey M Mason