Motorola Corporation

Freescale Semiconductor,inc.

Jeffrey M Finder

Kurt W Eisenbeiser

Ravindranath Droopad

William J Ooms

Zhiyi Jimmy Yu

Yu Wang

Ramoothy Ramesh

Bich-Yen Nguyen

Ramamoorthy Ramesh

Jamal Ramdani

Jerald A Hallmark

Hao Li

Barbara M Foley

Yong Liang

Corey D Overgaard

Danny L Thompson

An exemplary system and method for providing a microwave regime, frequency-agile device is disclosed as comprising inter alia: a low-loss, insulating substrate ( ); a layer of SiO ( ) over the surface of said substrate; and a layer of BST ( ) deposited over the SiO layer ( ). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize frequency response or other material characteristics. Exemplary embodiments of the present invention representatively provide for integrated high-efficiency, low-loss microwave components that may be readily incorporated with existing technologies for the improvement of frequency response, device package form factors, weights and/or other manufacturing, device or material performance metrics.

BST on low-loss substrates for frequency agile applications

A high quality epitaxial layer of monocrystalline Pb(Zr,Ti)O can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.

Microelectronic piezoelectric structure and method of forming the same

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.

Semiconductor structure including a partially annealed layer and method of forming the same

High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer ( ) is a layer of monocrystalline material spaced apart from the silicon wafer ( ) by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices ( ) on a monocrystalline silicon substrate.

Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same

High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer ( ) on a silicon wafer ( ). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer ( ) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Quantum well infrared photodetectors ( ) can be grown on the high quality epitaxial monocrystalline material formed on such compliant substrates to create highly reliable devices having reduced costs.

Quantum well infrared photodetector and method for fabricating same

High quality epitaxial layers of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Acoustic wave device and process for forming the same

A high quality epitaxial layer of monocrystalline Pb(Mg,Nb)O &mdash;PbTiO or Pb(Mg Nb )O &mdash;PbTiO can be grown overlying large silicon wafers by first growing an strontium titanate layer on a silicon wafer. The strontium titanate layer is a monocrystalline layer spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide.

A transistor ( ) and method of making an integrated circuit ( ) uses a chromium based sacrificial gate ( A) to align, dope and activate source and drain portions ( ) of the transistor. The transistor is subjected to a high temperature to activate the source and drain, which would damage a high permittivity gate dielectric. The sacrificial gate is removed by etching with ceric ammonia nitrate. A high permittivity gate dielectric ( ) and a final gate electrode ( ) are formed over a channel ( ) of the transistor. Electrodes ( ) are formed for coupling to the source and drain.

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Chandler, AZ, United States of America

Jeffrey M Finder