Advanced Micro Devices Corporation

Legerity, Inc.

Other

Jeffrey M Blumenthal

Ian S Crayford

Nader Vijeh

Larry David Hewitt

David E Norris

John M Wincn

Dale E Gulick

Paul G Schnizlein

Alfredo R Linz

David N Suggs

Carlin D Cabler

Glen W Brown

Geoffrey E Brehmer

Michael E Spak

Ryan E Feemster

Martin P Soques

Michael Hogan

David J Guercio

Alan T Torok

Dan Nichols

A accessory mounting system for use with gastrostomy buttons is herein described. The system consists of an accessory mounting platform and a cap that is able to be manually attached and detached from the accessory mounting platform. The accessory mounting platform can be integrally mounted to either the keeper strap or the head of the gastrostomy button, or it can be attached to the keeper strap of an existing gastrostomy button using a clip integrally attached to its underside.

Gastrostomy button accessory mounting platform

A method and apparatus is provided for clamping of an electrostatic discharge using multiple time-constants. A rise in a voltage level is detected. A first time-constant is provided to determine whether the rise in the voltage level is caused by an electrostatic event. A clamping function is provided to clamp the voltage level in response to a determination that the rise in the voltage level is caused by the electrostatic event. A second time-constant is provided to provide a time period for maintaining the clamping function for a period of time to substantially extinguish the electrostatic event.

Double time-constant for electrostatic discharge clamping

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.

Enhanced register array accessible by both a system microprocessor and a

A Built-In Self-Test (BIST) circuit and test method are employed for automated testing of a programmable analog gain stage. The BIST circuit and operating method advantageously use the natural redundancy of a multiple-channel circuit for detecting circuit faults. More specifically, the BIST circuit utilizes the natural redundancy of the identical signal paths for multiple-channel, such as stereo, audio operation. A left channel and a right channel ideally function identically so that a fault in one channel of the left channel and the right channel signal paths is detected by mutually comparing the operation of the two channels.

Apparatus and method for automated testing of a progammable analog gain

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (ETD) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

AUI to twisted pair loopback

Method and apparatus for squelch circuit in network communication

A differential receiver incorporated into a MAU which receives both Manchester packets and linkpulses according to the IEEE 802.3 10Base-T standard has polarity detection and correction circuit for automatically detecting a reversed polarity for RD input lines. The differential receiver samples incoming pulses for time, amplitude and pulse width qualification and makes a preliminary polarity determination based upon polarity of such qualified pulses. This preliminary polarity allows a linktest state machine to transition to a link.sub.-- pass state, enabling output drivers of the MAU. Additionally, the linkpulse polarity information initially makes a polarity determination for the entire differential receiver which asserts a FIX POLARITY signal. The FIX POLARITY signal controls a correction circuit which internally remedies reversed input lines. Preferably, the correction circuit internally reroutes the signals. An ETD polarity circuit makes polarity determinations from any ETD information received, as effected by the correction circuit. The ETD polarity circuit independently controls the linkpulse polarity determinations and conflicting determinations are resolved in favor of the ETD polarity circuit. Upon detecting two consecutive, consistent valid ETDs, the ETD polarity circuit locks-in the polarity determinations until a reset or a linkfail condition. The correction circuit effects both Manchester packets and linkpulses, so an incorrectly locked polarity will produce inverted linkpulses which will not allow the MAU to remain in the link.sub.-- pass state. In the linkfail state, the MAU may reestablish the correct polarity.

Automatic polarity detection and correction method and apparatus

An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (EDT) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

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Austin, TX, United States of America

Jeffrey M Blumenthal