Globalwafers Co., Ltd.

Memc Electronic Materials, Inc.

Sunedison Semiconductor Limited (uen201334164h)

Sunedison Semiconductor Limited

Jeffrey Louis Libbert

Igor Peidous

Gang Wang

Shawn George Thomas

Srikanth Kommu

Robert Wendell Standley

Lu Fei

Andrew Marquis Jones

Hariprasad Sreedharamurthy

Michael R Seacrist

Leif Jensen

Qingmin Liu

Robert J Falster

Mohsen Banan

Alex Usenko

Michael John Ries

Luciano Mule'Stagno

Gregory A Young

Richard Joseph Phillips

Henry Frank Erk

Steven Lawrence Kimbel

Sasha Joseph Kweskin

Milind S Kulkarni

Dale A Witte

Horacio Josue Mendez

Martin Jeffrey Binns

Igor Rapoport

Stephen J Brunkhorst

Mayank Bulsara

Samuel Christopher Pratt

Leslie George Stanton

Michelle Rene Dickinson

Chang Bum Kim

Joseph C Holzer

Charles Robert Lottes

Guoqiang David Zhang

Shilpi Vaypayee

Andrew M Jones

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

High resistivity silicon-on-insulator substrate comprising an isolation region

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability

Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate

A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

Methods for assessing semiconductor structures

Growing community of inventors

O'Fallon, MO, United States of America

Jeffrey Louis Libbert