Intel Corporation

Nanosys, Inc.

Sharp Kabushiki Kaisha Corporation

Sharp Microelectronics Technology, Inc.

Oned Material, Inc.

Jeffrey L Miller

James W Conary

David P DiMarco

David P Stumbo

Michael J Allen

Francisco A Leon

Jonathan H Liu

Hiroshi Iwata

J Wallace Parce

Akihide Shibata

Paul John Schuele

Xiangfeng Duan

Hiroshi Ohki

James M Hamilton

Katsumasa Fujii

Tetsu Negishi

Mahadevamurty Nemani

Samuel Edward Martin

Cheri X Y Pereira

Yasunobu Okada

Robert S Dubrow

Edward Allyn Burton

Francesco Lemmi

Stanley Steve Kulick

Sunit Tyagi

Erik Hallnor

Zhongying Zhang

David Dutton

R Kenneth Hose

Nivruti Rai

Dieter W Spaderna

Anshumali Kumar

Raul A Aguilar

A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.

Method and apparatus for cache line state update in sectored cache with line state tracker

The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Methods for formation of substrate elements

A dielectric material is disclosed comprising a plurality of substantially longitudinally oriented wires which are coupled together, wherein each of the wires includes a conductive core comprising a first material and one or more insulating shell layers comprising a compositionally different second material disposed about the core. In one embodiment, a dielectric layer is disclosed comprising a substrate comprising an insulating material having a plurality of nanoscale pores defined therein having a pore diameter less than about 100 nm, and a conductive material disposed within the nanoscale pores. Methods are also disclosed to create a dielectric material layer comprising, for example, providing a plurality of wires, wherein each of the wires includes a core comprising a first material and one or more insulating layers comprising a compositionally different second material disposed about the core; substantially longitudinally orienting said plurality of wires along their long axes; coupling the wires together; and depositing an insulating coating on at least one of a top and/or a bottom end of the wires.

Dielectrics using substantially longitudinally oriented insulated conductive wires

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Methods for nanowire alignment and deposition

Graded artificial dielectrics using nanostructures, such as nanowires, are disclosed. The graded artificial dielectric includes a material (typically a dielectric) with a plurality of nanostructures, such as nanowires, embedded within the dielectric material. One or more characteristics of the nanostructures are spatially varied from a first region within the dielectric to a second region within the dielectric to produce permittivity of the graded artificial dielectric that is spatially varied. The characteristics that can be varied include, but are not limited to, nanostructure density, nanostructure length, nanostructure aspect ratio, nanostructure oxide ratio, and nanostructure alignment. Methods of producing graded artificial dielectrics are also provided. A wide range of electronic devices such as antennas can use graded artificial dielectrics with nanostructures to improve performance.

Continuously variable graded artificial dielectrics using nanostructures

A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

Method and apparatus to lower operating voltages for memory arrays using error correcting codes

Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.

Memory array leakage reduction circuit and method

Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the address bus and the memory section. The tag RAM further includes a selection module coupled to the address bus and coupled to the comparator. The selection module selects one or more bits of the address field as tag field bits depending on the width of the address field and the size of the cache memory coupled to the tag RAM.

Tag RAM with selection module for a variable width address field

A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.

Detecting states of signals

Reducing timing variance of signals from an electronic device

Method and apparatus to monitor a characteristic associated with an electronic device

A synchronous interface to a self-timed memory array includes one or more address bus inputs and a first latch stage that includes one or more latches. Each of the latches of the first latch stage includes an input coupled to one of the address bus inputs and a first output. The synchronous interface further includes a second latch stage that includes a plurality of latches. Each of the latches of the second latch stage includes an input coupled to one of the first outputs of the first latch stage and a second output coupled to the memory array.

Synchronous interface to a self-timed memory array

A CPU is coupled to the cache memory over a system bus having a width of 64 data bits. The cache memory is organized into a left array and a right array, with data bits stored as lines of data wherein each line is comprised of 256 data bits defined into four data 'chunks' of 64 bits each. Each memory read access by the CPU to the cache results in a complete line of data to be read in the cache. The chunks comprising the line of data are coupled over an internal cache bus to a 'chunk' multiplexor. The chunk multiplexor stages the data chunks in an order defined by the CPU, and sequentially send the data chunks over the system bus to the CPU. The chunks are organized as high and low order chunks. The multiplexor includes a first multiplexor for receiving the high order chunks and a second multiplexor for receiving the low order chunks. Latches are provided which are coupled to the first and second multiplexors to receive the high order chunks upon the receipt of a first clock signal, and the low order chunks upon the receipt of a second clock signal. Enabling signals are provided to the latches such that the high order and low order chunks are coupled to the system bus in a sequential order which is determined by the CPU.

Cache memory having a multiplexor assembly for ordering output on a data

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Vancouver, WA, United States of America

Jeffrey L Miller