Motorola Corporation

Other

Jeffrey L Klein

Papu D Maniar

Chris C Yu

Robert W Fiordalice

Louis C Parrillo

Stephen S Poon

Wei E Wu

James R Pfiester

Philip J Tobin

Sudhir Kumar Madan

Rama I Hegde

Frank K Baker

Bernard J Roman

Dean J Denning

Tat-Kwan Edgar Yu

Duncan M Fisher

Mark S Swenson

Roc Blumenthal

Jeffrey F Hanson

A A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

Method for forming a conductive structure having a composite or

Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CMP using a slurry comprised of either copper sulfate (CuSO.sub.4) or copper perchlorate [Cu(ClO.sub.4).sub.2 ] and an abrasive, such as alumina or silica, and water. In another embodiment, a CMP process using such slurries may be used to form conductive interconnects (50) in a semiconductor device (40).

Method for chemical mechanical polishing a semiconductor device using

A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.

Method for forming a via in a semiconductor device

In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.

Method for forming inlaid interconnects in a semiconductor device

A conductive plug (46) is formed in a semiconductor device (30) by using an aluminum nitride glue layer (42). The glue layer is deposited on an interlayer dielectric (40) prior to forming a contact opening (44), such that the glue layer does not line the opening sidewalls or bottom. Tungsten or other plug material is then deposited in the opening and on the glue layer and subsequently polished or etched back to form the plug. The remaining portions of the glue layer may be left within the device or removed as deemed appropriate.

Method for forming a plug and semiconductor device having the same

A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

Process for fabricating a semiconductor device having an improved metal

Semiconductor device having an improved metal interconnect structure

A chemical-mechanical-polishing process in which acoustic waves are generated in the polishing slurry (18) to enable detection of an end-point in the polishing process, and to continuously clean the surface of a polishing pad (14) in a polishing apparatus (10). Acoustic waves are generated in the polishing slurry (18) by submerging a transducer (28) in the polishing slurry (18). The transducer (28) is powered by a voltage amplifier (30) coupled to a frequency generator (32). The frequency of the acoustic waves is adjusted by the frequency generator (32) to obtain optimum wave generation in the polishing slurry (18). The end-point of the polishing process is detected by a change in the acoustic wave velocity in the polishing slurry (18), which occurs when the slurry composition changes at end-point. The wave velocity is monitored by a receiver (34) submerged in the polishing slurry (18) at a predetermined distance from the transducer (28). Additionally, the acoustic wave frequency can be adjusted by the frequency generator (32) to induce sonic vibration in the polishing pad (14) such that continuous cleaning action is attained on the surface of the polishing pad (14).

Acoustically regulated polishing process

An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

LDD transistor process having doping sensitive endpoint etching

A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is formed and patterned overlying the first aluminum layer. The pattern in this tungsten layer will determine the pattern for the first level of metal interconnect to be formed later in the first aluminum layer. The tungsten layer is etched using the underlying first aluminum layer as an etch stop. A second aluminum layer is then formed overlying the patterned tungsten layer and the exposed regions of the first aluminum layer. In one continuous etching step the second aluminum layer is patterned and etched to form a pillar, and the first aluminum layer is etched to form the first level of metal interconnect in the semiconductor device using the pattern formed earlier in the tungsten layer and to expose regions of the oxide layer. A dielectric is deposited overlying the exposed regions of the oxide layer, the formed pillar, and the thin tungsten layer. This dielectric is etched back to expose the top of the pillar, and then a third aluminum layer is deposited overlying the dielectric to make electrical contact to the exposed surface of the pillar.

Method for forming self-aligned vias in multi-level metal integrated

A semiconductor process is provided for the formation of a very low resistance contact. After a straight wall contact is formed conventionally above a silicon substrate, a blanket metal barrier layer is deposited. A plurality of planar polysilicon layers are deposited above the metal barrier layer. The polysilicon layers have varying doping levels and are etched away. A byproduct gas of the etch reaction is monitored and the transition between polysilicon layers can be accurately noted. In this way, a layer of doped polysilicon is left above the metal barrier in the contact region. Metal may then be patterned over the entire structure to provide a low resistance reliable contact.

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Austin, TX, United States of America

Jeffrey L Klein