Intel Corporation

Jeffrey Krieger

Nasser A Kurd

Mark L Neidengard

Vaughn J Grossnickle

George Vergis

David W Browning

Xiang Li

Alexander Uan-Zo-Li

Tawfik M Rahal-Arabi

Jeffrey A Carlson

Jen-Tai Hsu

Fei Deng

Cliff C Lee

Raymond P Askew

Scott T Gardiner

Jorege P Rodriguez

Sofia C Hao

Christopher J Kelly

Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

Hybrid pitch through hole connector

Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Apparatus, system, and method for re-synthesizing a clock signal

An electronic device may include a plurality of voltage rails to provide voltages to components of a load, a plurality of voltage regulators, and a buck converter apparatus to separately couple to more than one of the plurality of voltage rails and to provide a voltage to at least a specific one of the voltage rails.

Electronic device having plurality of voltage rails

A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers are adjacent. Other structures and methods are also described and claimed.

Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces

A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Printed circuit board routing and power delivery for high frequency integrated circuits

A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e.g., a motherboard), with a surface-mounted electrical component (e.g., a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.

Decoupling structure and method for printed circuit board component

Growing community of inventors

Portland, OR, United States of America

Jeffrey Krieger