Cadence Design Systems, Inc.

Jeffrey Kim Ng

Thaddeus Clay McCracken

Joseph P Jarosz

Miles P McGowan

Tobing Soebroto

Nozar Nozarian

Adam R Traidman

An improved approach is described for identifying IP for an electronic design. The present approach can be used to handle situation where there may be difficulties in identifying which, if any, IP matches the desired requirements of an electronic design for which the IP is to be used or integrated. The search wizard of the present approach facilitates identification of IP for an electronic design. Expert systems and expert system services are provided for identifying IP blocks for an electronic design. Concierge-like services may be used to facilitate a connection between a consumer of electronic IP and the provider or vendor of the electronic IP in conjunction with the expert services.

Method and system identifying IP blocks and block suppliers for an electronic design

An improved approach is described for allowing designers to identify and utilize suitable IP for an electronic design. An architecture is provided that includes an IP portal and/or chip estimator to identify suitable IP from a catalog of IP, which is integrated with a hosted design environment to use and test that IP for the user's specific electronic design. An authorization mechanism may be used to control access to the IP from the IP catalog. This approach greatly enhances the probability that IP suppliers will be successfully connected with the target consumers of those IP blocks.

Method and system for providing an architecture for selecting and using components for an electronic design

An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.

Growing community of inventors

Cupertino, CA, United States of America

Jeffrey Kim Ng