International Business Machines Corporation

Quickturn Design Systems, Inc.

Other

Jeffrey Joseph Ruedinger

Scott Douglas Clark

Roy Glenn Musselman

Charles Ray Johns

Thomas M Gooding

David C Mckay

Thomas Arab Alexander

David Wayne Hill

David John Krolak

Jeffrey Douglas Brown

Kent Harold Haselhorst

Andrew P Wack

Scott Michael Willenborg

Michael Joseph Carnevale

Juergen Saalmueller

Dorothy Marie Thelen

Robert Neill Newshutz

Peter Rudolph

Christian Gerhard Zoellin

Michael Deindl

Robert Bryan Cook

Blake Johnson

Thomas K Pokrandt

Thomas Alexander

Christopher Paul Schieffer

Jeffrey Steven Graves

Hermann Schulze Scholling

Angelo Salvatore Grimaldi

Michael Arthur Snyder

Systems, computer-implemented methods and/or computer program products are provided for operating a quantum circuit on a set of qubits. According to an embodiment, a system can facilitate control of data transfer between two or more nodes. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a compilation component that compiles one or more communication paths between two or more nodes for transfer of yet-undetermined data along the one or more compiled communication paths. Alternatively and/or additionally, the computer executable components can comprise an interval boundary implementation component that can commonly set and trigger a successively repeating time point at two or more nodes to align performance at the two or more nodes of one or more quantum gate operations.

Communication coordination and node synchronization for enhanced quantum circuit operation employing a hybrid classical/quantum system

Systems, computer-implemented methods, and computer program products to facilitate mapping conditional execution logic to different quantum computing resources are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a compiler component that maps a logical reference to a quantum bit data structure in an instruction, to a first engine component, and a deployment component that deploys the first engine component to a first block controller component operatively connected to a first quantum computing resource, wherein the first engine component controls the first quantum computing resource based on the instruction.

Mapping conditional execution logic to quantum computing resources

Systems, computer-implemented methods, and computer program products to facilitate quantum state measurement logic used in a quantum state measurement backend process are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a stage control register component that defines a data processing function corresponding to at least one storage element in at least one stage of a quantum state measurement pipeline.

Quantum state measurement logic facilitating a quantum state measurement backend process

Systems, computer-implemented methods and/or computer program products are provided for facilitating time management of a quantum program at one or more nodes of a system, such as a hybrid classical/quantum system. A system, such as a classic portion of the hybrid system, can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a time management component that can communicate with a node to trigger the node to execute one or more quantum program instructions relative to a counter of the node that is advanced by the communicating. The time management component can advance the counter at the node based upon a combination of time of another node and of a determined actual propagation time for the communicating.

Time management for enhanced quantum circuit operation employing a hybrid classical/quantum system

Embodiments are provided for centralized control of execution of a quantum program. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a synchronization component that causes multiple controller devices remotely located relative to the system to be synchronized with one another and the system. The computer-executable components also include an ingestion component that accesses measurement data resulting from one or more measurements at respective qubit devices. The computer-executable components further include a composition component that generates, using the measurement data, one or more control messages for respective second controller devices of the multiple controller devices.

Centralized control of execution of quantum program

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Accelerating functional verification of an integrated circuit

A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

Envelope packet architecture for broadband engine

In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.

Triple voting cell processors for single event upset protection

An apparatus, circuit arrangement and method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Time multiplexed interface for emulator system

In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and (2) generating an error injection trigger indicating when the pseudo-random error is to be inserted. Numerous other aspects are provided.

Methods and apparatus for error injection

The present invention provides for dynamically determining a ratio of forwarded packets to injected packets to be transmitted in a bus ring. At least one forwarded packet is received into a first queue. An injected packet is received into a second queue. A determination, or snapshot, of the number of forwarded packets in the first queue due to the presence of the injected packet in the second queue is triggered. Packets corresponding to the snapshot are transmitted. After the packets are transmitted, if there is another injected packet stored in the second queue, another snapshot is performed. Packets corresponding to this snapshot are transmitted, and so on.

Method and system for ensuring arbitration fairness in bus ring topology

A method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

A method and apparatus are provided for implementing data mapping using a shuffle algorithm. An output shuffler and an input shuffler convert a physical data group to a plurality of data subgroups. The physical data group includes a plurality of bits and each subgroup includes a subplurality of bits. The output shuffler performs an output shuffle sequence for providing a predefined output pattern of ordered subplurality data bits. The predefined output pattern of ordered subplurality data bits is applied to the input shuffler. The input shuffler performs a reverse shuffle sequence. For each shuffle transfer a number of first header bytes of a packet are located at a first one of a plurality of physical layer links. Both the output shuffler and the input shuffler are implemented with minimized logic required to keep a largest multiplexer as a 4-to-1 multiplexer, resulting in minimal area and power being used for implementing the shuffle sequence and reverse shuffle sequence.

Method and apparatus for implementing data mapping with shuffle algorithm

The present invention provides for an integrated circuit (IC) bus system. A local IC is coupled to a remote IC through a bus interface. A local memory is coupled to the local IC. A bus interface controller is employable to track data transfer requests from the remote IC for data address that are contained within at least one segment of the first partitioned memory range. The bus interface controller is further employable to stop the forwarding of a data transfer request generated within the local IC to the remote IC, if the memory segment count corresponding to the data address of the locally generated data transfer request equals zero.

Bus interface controller for determining access counts

An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path. Locations in the buffer are associated with specific steps in the evaluation cycles of each of the transmitter and receiver clock domains, and the write/read pointers are managed to respectively write and read data to and from the locations in the buffer based upon the current evaluation steps being performed within the respective evaluation cycles of the transmitter and receiver clock domains.

Growing community of inventors

Rochester, MN, United States of America

Jeffrey Joseph Ruedinger