Micron Technology Incorporated

Micron Electronics, Inc.

Jeffrey Jay Rooney

Joseph M Jeddeloh

Dean A Klein

Richard F Nicholson

Douglas Alan Larson

Kirsten S Lunzer

Paul A LaBerge

Charles K Snodgrass

Travis E Swanson

Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

Programmable on-chip logic analyzer apparatus, systems, and methods

Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Integrated testing apparatus, systems, and methods

A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory controller register (MCR) and implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

Providing memory test patterns for DLL calibration

A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

System and method for dynamic buffer allocation

Dynamic buffer allocation for a computer system

One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines. This plurality of outputs is coupled to a first set of output pins on the semiconductor chip. The selector circuit is configured to select the first subset of grant lines to be driven through the first set of output pins during a first mode of operation, and is configured to select the third subset of grant lines to driven through the first set of output pins during a second mode of operation.

Apparatus for flexibly allocating request/grant pins between multiple bus controllers

One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.

Method for flexibly allocating request/grant pins between multiple bus controllers

A method for dynamically allocating buffers between components in a computer system is described. Matched sets of bidirectional buffers are used to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

System for dynamic buffer allocation comprising control logic for

An apparatus and a method are provided for delaying or skewing a control signal provided to an electronic device such as a memory device with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to the electronic device substantially equals one or more integral cycles of a clock signal. As a result, the control signal received at the electronic device is substantially aligned with the clock signal. This results in synchronizing or realigning the asynchronously-generated control signal back into a synchronous environment. The apparatus and method have unique applicability when used in memory controllers and the like for handling memory accesses with one or more memory devices, in particular with memory devices having enhanced memory transfer modes or higher transfer speeds, where even a small amount of skew between a control signal and a clock signal may significantly degrade performance. A propagation delay, or delay factor, associated with outputting the control signal to the electronic device is computed based upon the process factor for the apparatus, as well as any temperature and/or voltage variations. In addition, the delay factor may be modified dynamically to account for real-time voltage and/or temperature variations.

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Red Wing, MN, United States of America

Jeffrey Jay Rooney