Lsi Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Agere Syatems Inc.

Jeffrey Jay Nagy

Makeshwar Kothandaraman

John Christopher Kriz

Dipankar Bhattacharya

Bernard Lee Morris

Pankaj Kumar

Yehuda Smooha

Pramod Elamannu Parameswaran

Frank P Higgins

Ilyoung Kim

Stefan Allen Siegel

James Louis Lewandowski

Peter J Nicholas

Larry Ray Fenstermaker

A voltage translator circuit () includes an input stage () adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch () adapted for connection to a second voltage supply (VDD) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp () coupled between the input stage () and the latch (). The voltage clamp () is operative to set a maximum voltage across the latch () to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit () generates a first output signal (II) at a junction between the latch () and the voltage clamp (). The voltage translator circuit generates a second output signal () at a junction between the voltage clamp () and the input stage ().

Voltage level translator circuit

Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output ('I/O') buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

I/O buffer with low voltage semiconductor devices

Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Bias circuit scheme for improved reliability in high voltage supply with low voltage device

A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.

Reference compensation circuit

A memory device has first and second sets of memory cells. Each of the cells in the second set is a neighboring cell corresponding to a respective cell of the first set. A data generating function generates a first pattern and a second pattern. A controller causes the first pattern to be written in the first set of memory cells, causes each cell in the second set of memory cells to be read simultaneously while the corresponding neighboring cell in the first set of memory cells is being written to, and causes a datum to be read from each cell in the second set of memory cells after the corresponding neighboring cell in the first set of memory cells is written to. An output data evaluator determines whether the data read from the second set of memory cells match the second pattern, and detects a fault in the memory device, if the data read do not match the second pattern.

Method and system for testing multiport memories

Growing community of inventors

Allentown, PA, United States of America

Jeffrey Jay Nagy