University of California

Intel Corporation

Jeffrey J Peterson

Charles E Hunt

Jahanshir J Javanifard

Rodney R Rozman

Jerry A Kreifels

Christopher John Haid

Vishram P Dalvi

Jeff Evertt

Joseph W Tsang

David Dixon

Peter J Bjeletich

Dow Ping D Wong

Vishram Prakash Dalvi

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Block locking apparatus for flash memory

One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.

Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures

One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next, the system measures properties of the layer using electromagnetic radiation. The properties of the layer measured are used to determine an index of refraction for the layer. The system then solves for the composition of the layer using the index of refraction.

Method and apparatus for determining layer thickness and composition using ellipsometric evaluation

One embodiment of the present invention provides a system that facilitates construction of electromagnetic, optical, chemical, and mechanical systems using chemical endpoint detection. The system operates by receiving a system description that specifies multiple components, including a first component and a second component. The system fabricates the first component and the second component using selected construction materials. The system also creates a first interconnection structure on the first component and a second interconnection structure on the second component. These interconnection structures can be created using a sacrificial layer and chemical endpoint detection. Next, the system brings the first component and the second component together by connecting the first interconnection structure and the second interconnection structure. These interconnection structures align the first component to the second component so that accurate alignment can be achieved.

Fabrication of electronic magnetic, optical, chemical, and mechanical systems using chemical endpoint detection

One embodiment of the present invention provides a system to facilitate using selective etching to form optical components on a circuit device. The system operates by receiving a substrate composed of a first material including a buffer layer composed of a second material. The system forms a sacrificial layer composed of a third material on the buffer layer. Next, the system forms an optical fiber core composed of a fourth material on the sacrificial layer. After the optical fiber core has been formed, the system performs an etching operation using a selective etchant to remove the sacrificial layer. The system also applies a cladding layer to the optical fiber core.

Fabrication of optical components using Si, SiGe, SiGeC, and chemical endpoint detection

Programming a reference voltage in a reference cell of a charge-based memory to a level that will maximize the predicted operational life of the memory, based on the application-specific predicted usage profile of the memory and the effects of that usage profile on the leakage curves of the various memory states. The different states of a memory cell may have different leakage rates, based on operational and environmental considerations, causing the cell to fail prematurely in one state, while having significant remaining life in the other state(s). The operational life of the memory can be increased by adjusting the reference threshold voltage so that the faster-leaking sate will last longer before failure occurs. Maximum operational life can be achieved by setting the reference voltage to maximize the predicted time-to-failure of the state with the shortest predicted time-to-failure.

Setting data retention thresholds in charge-based memory

One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

Method and apparatus for fabricating structures using chemically selective endpoint detection

One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.

Method of fabricating three-dimensional components using endpoint detection

One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

Structures using chemo-mechanical polishing and chemically-selective endpoint detection

One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the a second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

Fabricating structures using chemo-mechanical polishing and chemically-selective endpoint detection

A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.

Block locking and passcode scheme for flash memory

A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Growing community of inventors

Folsom, CA, United States of America

Jeffrey J Peterson