Motorola Corporation

Jeffrey J Ogren

Thomas Michael King

Douglas W Schucker

Jeffrey Koeller

Richard M Povenmire

Francis Casey

A monolithic wireless receiver suitable for use in a global positioning system (GPS) or other radio frequency (RF) application suitably includes a mixed-mode integrated circuit and a stacked memory device. The mixed mode integrated circuit appropriately includes a digital portion and an analog portion on a common die. The analog portion implements an RF receiver circuit, and the digital portion includes a signal processor that communicates with the RF receiver. The memory device appropriately communicates with the integrated circuit to store electronic instructions and data for the signal processor. The monolithic receiver may be conveniently integrated into a portable electronics device such as a camera, personal digital assistant (PDA), portable phone or the like to provide location sensing or other RF functionality.

Wireless receiver with stacked, single chip architecture

A method of acquiring signal code phases includes selecting a correlation sum with a greatest magnitude from a set of correlation sums after a predetermined time has elapsed. A geographic positioning receiver performing the method includes two or more memory banks ( ) alternating between storing a signal sequence and transmitting the signal sequence to parallel correlators ( ) to be correlated against a predetermined pattern sequence for real-time data processing.

Method of acquiring signal code phases and geographic positioning receiver

A global position system (GPS) receiver for a host product is controlled by a microcontroller that also controls other functions in the host product. The GPS receiver includes an RF downconverter and a digital signal processor. The digital signal processor includes a correlator and an interface for asynchronously interfacing the correlator with the product's microcontroller. A monolithic integrated circuit includes RF downconverter circuitry, the correlator, and the interface for the GPS receiver.

Host-independent monolithic integrated circuit for RF downconversion and digital signal processing of GPS signals

A generic interface controller for a processor to peripheral device interface. This circuit eliminates marginal timing between a processor and a plurality of different peripheral devices while providing read and write operations within a minimum amount of cycle time. The processor interface controller generates read, write and acknowledge signals. This controller is particularly useful for ASIC applications where some of the peripheral devices such as memory, may be co-located on the ASIC circuit while other peripheral devices may be remotely located from the application Specific Integrated Circuit (ASIC) circuit.

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Mesa, AZ, United States of America

Jeffrey J Ogren