Intergraph Corporation

3dlabs Inc. Led.

Jeffrey J Holt

David W Young

James Leroy Deming

An improved device, of the type utilizing a display having pixels identified by a two-axis coordinate system, displays line segments referenced to the same coordinate system under control of a digital computer. The coordinate system, for example, having standard rectangular X and Y Cartesian coordinates, is configured so that each pixel lies at the intersection of a coordinate line from each of the axes. The improvement has an arrangement for determining as a major axis the axis of the coordinate system with respect to which the line moves most, and for defining the other one of the axes as the minor axis. For each major axis coordinate line crossing of the line segment, a pixel selection arrangement selects for display a pixel that both lies on the major axis coordinate line and has a minor axis coordinate that is closest to the line segment. In a further embodiment, the pixel selection arrangement includes a tie breaker for selecting for display, in accordance with a uniform rule, between two minor axis coordinates equidistant to the line segment. In a further embodiment, a second uniform rule determines whether to select a pixel for display when an end of the line segment lies exactly on the major coordinate line of a pixel. The second uniform rule selects for display one of the first and last pixels of a line segment unless the line segment is isolated and unless the line segment lies at a specified end of a series of connected segments.

Efficient stroking of vectors with arbitrary endpoints

A system and method for controlling a slave processor from a master processor in which the slave processor is instructed to await the occurrence of a particular event and the arrival of a number of data words before processing additional requests. A wait request from the master processor includes identification of an event which must occur before processing is to resume. The master processor provides a number to a register accessible to the slave processor to indicate how many data words to await. The slave processor discontinues processing upon receiving the wait request. The slave processor detects the occurrence of the event and the arrival of the data words and then resumes processing. The register may include an indicator or flag that indicates when the number of data words set by the master processor has been received.

System and method for controlling a slave processor

A 3D graphics processing system in a preferred embodiment has an input for a digital video data stream. The system has a graphics engine, for processing graphics request code and data, in communication with a host computer over a data bus and also in communication with a frame buffer. It also has an input for a digital video data stream, and the input is in communication with the graphics engine. A control arrangement interrupts processing by the graphics engine of conventional graphics request code and data to permit priority processing of the digital video data stream. In this manner, an image associated with the digital video data stream may be displayed in real time in a desired plane that may be accessed and processed by the graphics processing system as a graphic image. In a further embodiment, the control arrangement is operative to interrupt processing by the graphics engine at a span break and the image associated with the digital video data stream and processed by the graphics engine is stored in the frame buffer.

Video stream data mixing for 3D graphics systems

A device is provided for managing vertex lists. In particular, in one embodiment, the device permits management of the communication, in a digital computing system having a graphics processor, of a sequence of data records associated with successive vertices. The vertex data are typically used for drawing polyline figures or triangular mesh, or other figures using coordinates. Each record includes at least one floating point value that provides at least a first datum associated with a vertex. The device comprises an arrangement for placing the sequence of data records in a data stream, as well as an arrangmement for placing at the end of the data stream a data record in which the floating point value providing the first datum is set to a value corresponding to Not a Number. In this manner it can be established when the sequence of records is complete without the need for any extra control bits. Related methods are also provided.

Vertex list management system

An improved graphics processor is of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine. The buffer is also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine. The improvement in a preferred embodiment utilizes a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer. User access via an application is provided only to the normal FIFO, whereas system level code is provided access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor. In a further embodiment, a logical sync FIFO is employed also. The sync FIFO is used in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing. Related methods are also provided.

Growing community of inventors

Madison, AL, United States of America

Jeffrey J Holt