Lsi Corporation

Lsi Logic Corporation

Jeffrey J Gauvin

Wiliam Petty

Stephen B Johnson

Gabriel Leandro Romero

Christopher McCarty

A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Back-off retry with priority routing

A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address register. After the sequence has executed, the address register is queried and the thread may continue. Many different threads may call the sequence. In more complex hardware implemented state machines, the total number of gates may be reduced significantly.

Common state sequences in a finite state machine

Disclosed is a process for controlling the expander cores of a dual expander using a single test port, such as a J-tag port. Access to and control of each expander core is accomplished by placing one of the cores in a bypass mode and accessing and controlling the other core through data supplied serially through the J-tag port.

Methodology for performing register read/writes to two or more expanders with a common test port

A bus interface and a receiver in the bus interface receive signals from a computer bus, such as a SCSI (Small Computer System Interface) bus, and deskew and synchronize the signals into valid data and control signals. The signals are aligned and then a portion of the signals is offset to ensure that the other signals have sufficient time to stabilize before being latched. The alignment is performed by adding and subtracting delay units to and from the signals. The offset is determined by a self-calibration logic that uses the same type of delay units.

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Colorado Springs, CO, United States of America

Jeffrey J Gauvin