Micron Technology Incorporated

Jeffrey J Cronin

Douglas Alan Larson

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Method and system for terminating write commands in a hub-based memory system

A method for terminating a bus configured to have one or more processors coupled thereto. The method comprises coupling a support member having a termination circuit thereon to a conductor of the bus. In one embodiment, the support member is connected to the bus separately from the processor. In another embodiment, the support member is coupled between the bus and the processor. The support member may include an auxiliary circuit in addition to the termination circuit and may be used to correct, supply, or update signals transmitted on the bus.

Method for terminating a processor bus

A device for terminating a bus configured to have one or more processors coupled thereto. The device comprises a support member having a termination circuit which is coupled to a conductor of the bus when the support member is coupled to the bus. In one embodiment, the support member is coupled between the bus and the processor. In another embodiment, the support member is connected to the bus separately from the processor. The support member may include an auxiliary circuit in addition to the termination circuit which may be used to correct, supply, or update signals transmitted on the bus.

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Andover, MN, United States of America

Jeffrey J Cronin