Intel Corporation

Other

Jeffrey J Cook

Deborah T Marr

Paul Caprioli

Jonathan D Pearce

David B Sheffield

Eriko Nurvitadhi

Asit K Mishra

Srikanth T Srinivasan

Koichi Yamada

Joseph Nuzman

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Edward Thomas Grochowski

Thomas D Fletcher

Stephen R Van Doren

Lokpraveen B Mosur

Narayan Ranganathan

Dennis Ryan Bradford

Kent D Glossop

Niall D McDonnell

Richard J Greco

Ganesh Venkatesh

Ruchira Sasanka

Dwight P Manley

Tracy Garrett Drysdale

Jayaram Bobba

Nicholas P Carter

Michael A O'Hanlon

Abhijit Davare

Elmoustapha Ould-Ahmed-Vall

David J Sager

Amit Bleiweiss

Srinivas Sridharan

Dheevatsa Mudigere

Suresh Srinivas

Dhawal Srivastava

Andrey Ayupov

Anavai Ramesh

Mohammad Ashraf Bhuiyan

Anton Alexandrovich Sorokin

Md Faijul Amin

Niharika Maheshwari

Abhinav Das

Abhay Kanhere

Arvind Krishnaswamy

Muawya M Al-Otoom

Steven Burns

Desmond A Kirkpatrick

Wei W Wang

Youfeng Wu

Ron Gabor

Wei D Wang

Shlomo Raikin

Wei Wang

Tin-Fook Ngai

Jason M Agron

Ho-Seop Kim

Michael R Greenfield

Omar M Shaikh

Leeor Peled

Howard Chen

Debbie Marr

Jason A Domer

Keith M Sayre

Rishiraj A Bheda

Furat F Afram

Shreesha Srinath

Ching-Kai Liang

Niall D Mcdonnell

Michael A O'HANLON

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Apparatus and method for adaptable and efficient lane-wise tensor processing

In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.

System, apparatus and method for symbolic store address generation for data-parallel processor

Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a translation cache. The cost-benefit metric is indicative of translation cost and performance benefit associated with the translated code block. The translation cost may be determined by measuring translation time of the translated code block. The cost-benefit metric may be calculated using a weighted cost-benefit function based on an expected workload of the computing device. In response to determining to free space in the translation cache, the computing device determines whether to discard each translated code block as a function of the cost-benefit metric. In response to determining to free space in the translation cache, the computing device may increment an iteration count and skip each translated code block if the iteration count modulo the corresponding cost-benefit metric is non-zero. Other embodiments are described and claimed.

Technologies for translation cache management in binary translation systems

An apparatus and method for offloading iterative, parallel work to a data parallel cluster. For example, one embodiment of a processor comprises: a host processor to execute a primary thread; a data parallel cluster coupled to the host processor over a high speed interconnect, the data parallel cluster comprising a plurality of execution lanes to perform parallel execution of one or more secondary threads related to the primary thread; and a data parallel cluster controller integral to the host processor to offload processing of the one or more secondary threads to the data parallel cluster in response to one of the cores executing a parallel processing call instruction from the primary thread.

Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency

In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.

Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor

An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Architecture and method for data parallel single program multiple data (SPMD) execution

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule a plurality of matrix operations responsive to a tensor matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, each lane comprising: first, second, and third tile registers to store blocks of a first matrix (A), second matrix (B), and third matrix (C), respectively; at least one tensor arithmetic logic unit (TALU) to multiply a block of elements of the first matrix with a block of elements of the second matrix to generate a product and to accumulate the product with a block of elements of the third matrix, wherein each lane is to multiply one or more different blocks of the first and second matrix and to accumulate the resulting one or more products with one or more different blocks of the third matrix; and broadcast circuitry to broadcast one or more invariant matrix blocks to different tile registers within a lane and/or different tile registers across different lanes.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Growing community of inventors

Portland, OR, United States of America

Jeffrey J Cook