International Business Machines Corporation

Globalfoundries Inc.

Jeffrey J Brown

Chienfan Yu

Qingyun Yang

Len Yuan Tsou

Yun-Yu Wang

Hussein Ibrahim Hanafi

Wesley Charles Natzle

George A Kaplita

David V Horak

Keith Kwong Hon Wong

Ying Di Zhang

Richard Stephan Wise

Maheswaran Surendra

Hongwen Yan

Ahmad D Katnani

Stefan Schmitz

Rebecca D Mih

Joyce C Liu

Sadanand Vinayak Deshpande

John W Golz

Jin J Wu

Christopher N Collins

Teresa Jacqueline Wu

Michael Joseph MacDonald

Kenneth A Bandy

Jochonia N Nxumalo

Senthil K Srinivasan

Daniel P Stambaugh

James C Brighten

Dimitrios Ioannou

Wilson Tong Lee

Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Mitigation of hot carrier damage in field-effect transistors

Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level is formed that includes a conductive feature. A dielectric layer is formed on the metallization level. The dielectric layer includes an opening that extends vertically through the dielectric layer to the conductive feature. An adhesion layer is formed on area of the conductive feature exposed at a base of the opening. The adhesion layer has a thickness equal to a monolayer or a fraction of a monolayer. Another layer (e.g., barrier layer) of a different composition (e.g., TiN) may be deposited on the adhesion layer before the opening is filled with metal deposited by chemical vapor deposition.

Liner replacements for interconnect openings

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Damascene double-gate MOSFET with vertical channel regions

A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process. The invention forms a passivating layer on exposed vertical surfaces of the conductive layer and completely etches unprotected portions of the conductive layer to expose the substrate. The invention then dopes exposed portions of the substrate to form source/drain regions.

Method to form gate conductor structures of dual doped polysilicon

A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si&mdash;C-containing film or combinations thereof.

Method to controllably form notched polysilicon gate structures

A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Dual mask process for semiconductor devices

A cleaning wafer is used during the vaporization of particulate deposits that were previously deposited on the walls of a plasma chamber. The cleaning wafer includes a first dielectric layer, a conducting layer and a second dielectric layer covering the conducting layer.

Universal cleaning wafer for a plasma chamber

Growing community of inventors

Fishkill, NY, United States of America

Jeffrey J Brown