Hayes Microcomputer Products, Inc.

Jeffrey Inskeep

George R Thomas

An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by the NCSROM conductor (41) and the NCSRAM conductor (40), respectively, so that the read only memory and the random access memory do not compete for control of the data bus (20). However, the NCSRAM conductor (40) is not used to control the random access memory during write operations. Therefore, when transferring blocks of data from the read only memory (60) to the random access memory (61,62) the NCSROM conductor (41) is active during both reading of data from the read only memory (60) and writing of the data to the random access memory (61). Since the NCSROM conductor (41) is active during both read and write operations, and since data can be written into the random access memory (61) by activating the NWR conductor (24), it can be said that the data transfer occurs, figuratively, by reading from the read only memory and then 'writing' to the read only memory. A pair of flip-flops (76,77) are used in conjunction with the NMREQ signal (26) to activate the hidden refresh feature of the selected random access memory (61, 62). This allows for refreshing of a larger random access memory than is otherwise supported by the refresh feature provided by the processor (10). The high and low order bytes of the address bus (21) are reversed to the electrically erasable and programmable memory (63) so that fewer instructions are required to transfer quantities of data to the memory (63) using the page write feature of the memory (63). The result is a memory control and refresh apparatus which uses fewer components and accomplishes transfers of data using fewer instructions.

Method for memory addressing and control with reversal of higher and

An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by a signal on conductor (41) and a signal on conductor (40), respectively, so that the read only memory and the random access memory do not compete for control of the data bus (20). However, the signal on conductor (40) is not used to control the random access memory during write operations. Therefore, when transferring blocks of data from the read only memory (60) to the random access memory (61,62) the signal on conductor (41) is active during both reading of data from the read only memory (60) and writing of the data to the random access memory (61). Since the signal on conductor (41) is active during both read and write operations, and since data can be written into the random access memory (61) by activating the NWR (negated write) signal on conductor (24), it can be said that the data transfer occurs, figuratively, by reading from the read only memory and then 'writing' to the read only memory. A pair of flip-flops (76,77) are used in conjunction with the NMREQ (negated memory request) signal (26) to activate the hidden refresh feature of the selected random access memory (61, 62). This allows for refreshing of a larger random access memory than is otherwise supported by the refresh feature provided by the processor (10). The high and low order bytes of the address bus (21) are reversed to the electrically erasable and programmable memory (63) so that fewer instructions are required to transfer quantities of data to the memory (63) using the page write feature of the memory (63). The result is a memory control and refresh apparatus which uses fewer components and accomplishes transfers of data using fewer instructions.

Method and apparatus for refreshing a dynamic memory

A memory (90) comprising a non-volatile memory and a volatile memory, contains a test word and other words which represent a complete user-selected configuration profile. The configuration profile is stored in the memory (90) by a microprocessor (36) automatically when power is interrupted. A second power supply (80) provides operating power to the memory (90) so that the memory (90) can complete its storage cycle even after primary power has failed. The microprocessor (36) checks memory (90) for the test word to verify that the memory (90) has been programmed with a configuration profile and is not missing or defective. The modem (12) resets when power is first applied and when the power supply (75) noise exceeds a predetermined safe level. A concealed jumper strap (61) allows for the reversible placement of the modem (12) into a 'dumb' mode wherein the configuration profile cannot be altered.

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Marietta, GA, United States of America

Jeffrey Inskeep