Iq Systems, Inc.

Iq Net Solutions, Inc.

General Datacomm, Inc.

Logic Devices Incorporated

Star Semiconductor Corporation

Other

General Datacomm Industries, Inc.

Jeffrey I Robinson

Keith Rouse

Terry F Montlick

Andrew J Krassowski

Bruce R Musicus

An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. According to the invention, instantiated objects communicate directly with a script server which is programmed to react to data events generated by instantiated objects. One script server may serve several object oriented processor arrays, or an object oriented processor array may have a local script server. The object oriented processor array may be embodied in hardware, software, or a combination of hardware and software. Each functional object may include a discrete hardware processor or may be embodied as a virtual processor within the operations of a single processor. According to one embodiment, the object oriented processor array is formed on a single chip or on a single processor chip and an associated memory chip.

Central and distributed script servers in an object oriented processor array

An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. The object oriented processor array may be embodied in hardware, software, or a combination of hardware and software. Each functional object may include a discrete hardware processor or may be embodied as a virtual processor within the operations of a single processor. According to one embodiment, the object oriented processor array is formed on a single chip or on a single processor chip and an associated memory chip. When several objects are instantiated on a single chip, pins may be assigned to each object via a high level command language. Methods and apparatus for allocating memory to instantiated objects are disclosed. Methods and apparatus for scheduling when several virtual processors are embodied within the operations of a single microprocessor are also disclosed.

Object oriented processor arrays

A distributed processing system includes a plurality of cells where each cell processes information in response to a type of event, and cells communicate with each other according to an (asynchronous) event-reaction protocol. Cells maintain mailing lists which are associated with events and which indicate the address(es) of cell(s) to whom a message is sent in response to the event. According to one embodiment, at least one cell is provided with the ability to read, write, and delete any address on any mailing list in the system. According to another embodiment, at least one cell keeps a list of events (subscription list) that are deemed important by the user where it is the cell's responsibility to insure that it remains subscribed to the mailing lists associated with these events. According to another embodiment, at least one cell serves more than one mailing list and preferably keeps a list of the mailing lists it serves. This cell also has the ability to move subscribers from one mailing list to another, to modify which mailing list is the currently active mailing list or to make a plurality of mailing lists simultaneously active. According to another embodiment, at least one cell has the ability to modify the subscription list of another cell. The invention is illustrated by example with reference to a PBX system.

Distributed processing systems incorporating a plurality of cells which process information in response to single events

The apparatus of the invention (a) monitors a subscriber line for the presence of DTMF tones, (b) intercepts DTMF tones by transmitting a set of DTMF harmonics onto the subscriber line, (c) detects the intercepted DTMF tones and records them or the digits they represent, (d) analyzes the intercepted digits to determine whether a long distance number has been dialed, and (e) if a long distance call has been dialed, transmits onto the subscriber line a DTMF signal which includes the intercepted DTMF signal plus a service provider access code DTMF signal inserted before it. According to a presently preferred embodiment, the apparatus includes a voltage sensor which detects a drop in voltage whenever a phone connected to the same subscriber line as the apparatus goes off-hook. The voltage detector turns the apparatus &ldquo;ON&rdquo; when an off-hook condition is detected. The preferred apparatus also includes an energy sensor which rapidly detects the presence of any fixed frequency tone and triggers a harmonics tone generator which preferably generates second harmonics of each of the &ldquo;row frequencies&rdquo;. Thus, all DTMF tones are blocked before they are recognized.

Methods and apparatus for intercepting dual-tone multi-frequency (DTMF) signals and for redialing the intercepted signals with additional DTMF signals

A distributed processing system includes a plurality of cells where each cell processes information in response to a type of event, and cells communicate with each other according to an (asynchronous) event-reaction protocol. According to one embodiment, each cell is responsive to a single type of event and includes a plurality of scripts which are executed upon the occurrence of an event of the appropriate type. At least some scripts include directions to send information to one or more scripts in another cell. According to another embodiment, some cells communicate with other cells according to a (synchronous) streaming protocol and other cells communicate according to an (asynchronous) event-reaction protocol. The cells communicate with each other via a shared memory or via a communications bus. The communications protocol utilized by the cells enables the use of virtually any networking medium. Thus, cells may reside in the same chip or may be separated from each other by thousands of miles.

PBX system having line cards and phone cards which exhibit reciprocal relationships

Distributed processing systems incorporating processing zones which communicate according to both streaming and event-reaction protocols

Distributed processing systems having self-advertising cells

Distributed processing systems including processing zones which subscribe and unsubscribe to mailing lists

Distributed processing systems incorporating nodes having processing cells which execute scripts causing a message to be sent internodally

An apparatus architecture is provided which permits an easily programmed apparatus (,) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (,) is connected to a communications bus (,) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (,), a core (,), and a parametric/microinstruction bus (,). The functional blocks include serial (,) and parallel ports (,), D/A (,) and A/D (,) converters, and programmable signal processors (,) which serve to process signal data and are connected in any desired manner through a switching matrix (,) located in the core. The topology of the switching matrix (,) is received via the communications bus (,). Parameters and microinstructions for the programmable signal processors (,) are sent via the communications bus (,), the core (,), and the parametric/microinstruction (,) bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports (,) and via the D/A and A/D (,) converters of the apparatus. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the apparatus.

Programmable digital signal processor integrated circuit device and method for designing custom circuits from same

The invention provides a distributed processing system having a host processor and one or more object oriented processors which are embodied as discrete components and as a collection of components on a single ASIC chip. A high level command language and a communications bus system are also provided both for use with discrete components and as an integral part of an ASIC chip. The ASIC chips are premanufactured to operate identically to a corresponding collection of discrete components. A distributed processing system is developed by coupling a collection of discrete object oriented processors and a host processor to a bus and writing a command language script to define the functionality of the system. After the system is designed and tested using discrete components, a suitable premanufactured ASIC or collection of ASICs is chosen and coupled to a host processor. The high level command language script permits the host processor and the ASIC system to perform identically to the discrete component system. An addressing scheme is provided in the command language such that multiple object orient processors may be given a single simultaneous command. Object oriented processors may have child ports with soft addressability to which other object oriented processors may be coupled. The child ports with soft addressability have software assignable addresses.

Methods and apparatus for distributed processing and rapid ASIC

An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. According to the invention, communication is based on an 'event-reaction' model. According to the event-reaction model, when a processor object has a message to send, it generates a data event which is registered with the target recipient of the message (usually the host). The target reacts to the event by allowing a variable amount of I/O exchange between the processor object and the target prior to an acknowledgement of the data event. According to one embodiment, until the data event is acknowledged, no other data event may be sent to the target. According to another embodiment, a fixed number of data events may be pending simultaneously. In one embodiment of a multi-node system, each node (each object oriented processor array) is aware of network traffic and data events related to a particular target (host) receiver are registered with all nodes which have that receiver as a target as well as with the target. The number of data events which may be simultaneously pending at any time is determined by the target and known to each of the nodes. The target arbitrates the flow of messages based on the registration of data events.

Event-reaction communication protocol in an object oriented processor

A self-timed high speed data communications system includes an N-bit wide data path and a three-bit wide event path. Six states of the event path are used to indicate when data is on the data path for reading and when the data path is available for transmission of data. In a presently preferred embodiment, the event path has three stable states and three meta-stable states. The initial state of the event path is a first stable state. When a user places data on the data path, the event path assumes a first meta-stable state. After the data is read by all users, the event path assumes a second stable state. Further transmission and reception of data cycles the event path through alternating meta-stable and stable states. The event path is preferably zero dominant (one recessive) and stable states are indicated when only one of the three bits are asserted by all users. Meta-stable states are indicated when a transmitting user asserts one bit of the event path and at least one other users asserts another bit of the event path. Acknowledgement of data reception by each user is signalled by the user de-asserting a bit of the event path. Both wired and wireless communications systems are disclosed. Several wireless signalling systems include coherent and non-coherent systems, FSK systems and pulse keyed systems. Apparatus for the wired and wireless systems are also disclosed. Efficient software implementation of the invention is also disclosed.

Methods and apparatus for implementing high speed data communications

Distributed processing systems having a host processor and at least one object oriented processor are disclosed. An object oriented processor according to the invention has a communications interface, an intelligent message handler, and a task-specific functionality. The communications interface is coupled to a host processor via a message based communications link. A high level command language is provided which is easily implemented in a host processor program. The command language includes subsets of commands which are understood by different object oriented processors having different functionality. According to one embodiment, the object oriented processor includes support for a broad array of input and output devices. The command language includes high level commands for initializing, reading from and/or writing to the peripherals supported by the object oriented processor. According to another embodiment, the object oriented processor of the invention is addressable and several object oriented processors having similar functionality can be coupled to a single host via the same comms link. According to yet another embodiment, an object oriented processor according to the invention further includes a linking table and a periodic message generator which allows one object oriented processor to communicate directly with another object oriented processor without supervision by the host processor.

Growing community of inventors

New Fairfield, CT, United States of America

Jeffrey I Robinson