International Business Machines Corporation

Newisys, Inc.

Jeffrey Holland Gruger

Gary Dale Carpenter

Sanjay Raghunath Deshpande

Manuel Joseph Alvarez, Ii

Peter Dau Geiger

Kai Cheng

Jin Chin Wang

William G Kupla

Manuel Alvarez

The present invention provides devices and techniques for replacing at least one processor in a multi-processor computer system with an interposer device that maintains at least some of the input/output ('I/O') connectivity of the replaced processor or processors. Layers of the interposer device may be configured to match the corresponding layers of the motherboard to which the processors and interposer device are attached. According to some implementations of the invention, the power system of the motherboard is altered to allow a voltage regulator that powers a link between a processor and the interposer device to also power a link between the interposer device and an I/O device.

Interposer device

A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses. The memory subsystems contain a memory controller and a fixed delay pipe from the address port to the memory controller so that the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.

Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors

A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.

Method and system for implementing parity error recovery schemes in a

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Austin, TX, United States of America

Jeffrey Holland Gruger