International Business Machines Corporation

Globalfoundries Inc.

Lenovo (singapore) Pte. Ltd.

Jeffrey Haskell Derby

Gordon Taylor Davis

Malcolm Scott Ware

Hua Ye

Robert K Montoye

Dongming Hwang

Youssef Abdelilah

Evangelos Stavros Eleftheriou

Dheeraj Sreedhar

Fredy Daniel Neeser

Clark Debs Jeffries

Ajay Dholakia

Bartholomew Blaner

Ken Van Vu

John E Drake, Jr

Sedat Oelcer

Brian Mitchell Bass

Marcia Lambert Peters

Marc Adam Kaplan

Roch A Guerin

Joseph Gerald McDonald

Kenneth Harvey Potter, Jr

Ross Boyd Leavens

George William Daly, Jr

Gerald Arnold Marin

Uzi Shvadron

John G Dudley

Willibald A Doeringer

David R Thomas

Haldon J Sandick

Vadim Sheinin

Srinivasan Ramani

Anil Krishna

Peter George Capek

Shay Ben-David

Ayal Zaks

Levent Gun

Hangu Yeo

Steven Paul VanderWiel

Joseph Franklin Garvey

Douglas H Dykeman

Gordon Bernard Bell

Charles Robert Young

Liang Li

Jamie H Moreno

Youseff Abdelilah

Steve Woolet

Alper Buyuktosunoglu

Pradip Bose

Todd Edward Takken

Michele M Franceschini

Claude R Galand

Bruce Martin Fleischer

Yutaka Nakamura

Thomas Winters Fox

Xin Zhang

Victor V Zyuban

Charles D Johnson

Israel Cidon

Allen Leonid Roginsky

Charles Luther Johnson

Diana Lynn Orf

Michael J Healy

Harold D Dykeman

Inder Sarat Gopal

Shay Kutten

James P Janniello

Aharon Satt

Jason A Viehland

Prashant Jayaprakash Nair

Martin Cochet

Augusto J Vega

David William Davenport

Theodore E Tedijanto

Robert John Schule

Francis R Koperda

Robert F H Fischer

Michelle Chan Granholm

Kevin Tien

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.

Hardware accelerator with locally stored macros

Single error correction ('SEC') code and triple error detection ('TED') code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.

Vector cross-compare count and sequence instructions

A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

Local computation logic embedded in a register file to accelerate programs

Methods, systems and computer program products for accelerating sorting of data are provided herein. A computer-implemented method includes retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements, scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions, forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered to the corresponding one of the plurality of bins, writing the bin cache line from the corresponding one of the plurality of bins to a memory, and loading the bin cache line from the memory to the input buffer.

In-memory/register vector radix sort

Methods and arrangements for joining data sets. There are accepted: a first data set which forms a table in a relational database, and a second data set which forms a table in a relational database, each of the first and second data sets comprising a key value. Each of the first and second data sets is hashed based on the key value, and are thereupon sorted based on the key value. The sorted first and second data sets are joined with one another based on the key value. Other variants and embodiments are broadly contemplated herein.

Sort-merge-join on a large architected register file

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

High-performance hash joins using memory with extensive internal parallelism

Methods, systems, and articles of manufacture for merging and sorting arrays on a processor are provided herein. A method includes splitting an input array into multiple sub-arrays across multiple processing elements; merging the multiple sub-arrays into multiple vectors; and sorting the multiple vectors by comparing and swapping one or more vector elements among the multiple vectors.

Merging and sorting arrays on an SIMD processor

A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines

In one embodiment, a method includes receiving a signal having communication data from two or more mobile devices, each identifiable by an associated pseudonoise sequence. A first mobile device is identifiable by a first pseudonoise sequence. Two or more samples of the received signal are stored in an input register. A segment of the first pseudonoise sequence is stored as a bit vector in a second register. The SIMD instruction is processed, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence and the samples of the received signal. Processing the SIMD instruction includes distributing the segment of the first pseudonoise sequence, as a bit vector, across two or more lanes of the SIMD processor. The processing contributes to despreading the received signal, and an output of the processing includes at least a portion of the communication data from the first mobile device.

Correlating pseudonoise sequences in an SIMD processor

Growing community of inventors

Chapel Hill, NC, United States of America

Jeffrey Haskell Derby