Qualcomm Incorporated

Hangzhou Fabu Technology Co., Ltd.

Jeffrey Hao Chu

Dexter Tamio Chun

Bohuslav Rychlik

Hang T Nguyen

Rahul Gulati

Subrato Kumar De

Serag Gadelrab

Richard Alan Stewart

Meghal Varia

David A Strasser

Hyukjune Chung

Eric Demers

Sudeep Ravi Kottilingal

Raghavendra Nagaraj

Xiaofei He

Aravind Bhaskara

Scott Cheng

Tao Shen

Wenbiao Wang

Alex Jong

Jun Liu

Pooja Sinha

Ujwal Patel

Nishant Hariharan

Ruo Long Liu

Sina Gholamian

Reza Kakoee

Mohit Bhave

In an embodiment, a camera sensor module is communicatively coupled to a vision processing system. The camera sensor module captures a plurality of exposures, produces an HDR-combined stream, and sends both the HDR-combined stream and the plurality of exposures to the vision processing system. A first ISP of the vision processing system performs color processing to produce a color-processed HDR-combined stream for neural network processing, presentation to a human, and/or computer vision processing. At least one other ISP of the vision processing system performs color processing to collect exposure-specific statistics on at least one of the plurality of exposures for determining camera calibration data for the camera sensor module.

Exchanging an HDR-combined stream and associated exposures between a camera sensor module and a vision processing system

Examples disclosed herein provide mechanisms for controlling a sensor in a multiple System on Chip (SoC) environment that allows one of the multiple System on Chips to be selected as a host System on Chip. The host System on Chip may lock the sensor to apply setting updates only from the host System on Chip that has locked the sensor. This lock may be broadcast to all sensors over an embedded data channel sent to all System on Chips receiving the sensor data. In addition, a safety monitor may be included to detect if the host System on Chip is functioning properly so that another System on Chip may be selected as a new host System on Chip.

Apparatus and method of sharing a sensor in a multiple system on chip environment

The present disclosure provides a method for checking a to-be-checked signal and related products. The method is applied in a checking device and includes: a first obtaining module, configured to obtain a to-be-checked signal carrying first control information, wherein the first control information is generated based on original control information; a second obtaining module, configured to obtain original checking information; a determining module, configured to determine the first control information according to the to-be-checked signal; and a checking module, configured to check correctness of the first control information according to the original checking information. The present disclosure can be used to enable reliability and functional safety on devices originally designed without features intended to support those functions.

Method for checking address and control signal integrity in functional safety applications, related products

Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.

System and method for controlling memory frequency using feed-forward compression statistics

Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Image signal processor data traffic management

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes encoding data at the EU. The method includes generating control data for decoding the encoded data at the EU. The method includes directing storage of the encoded data in the DRAM. The method includes directing storage of the control data in an on-chip memory separate from the DRAM, wherein the on-chip memory is on a same chip as the EU.

Bus encoding using on-chip memory

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit (EU) of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes compressing data at the EU. The method further includes encoding the compressed data at the EU. The method further includes generating control data for decoding the encoded data at the EU. The method further includes generating metadata corresponding to the compressed data at the EU. The metadata further includes the control data. The method further includes directing storage of the encoded data and the metadata in the DRAM.

Bus encoding using metadata

Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

Transaction elimination using metadata

Growing community of inventors

San Diego, CA, United States of America

Jeffrey Hao Chu