Xilinx, Inc.

Xlnx, Inc.

Jeffrey H Seltzer

David Chiang

Khang Kim Dao

Napoleon W Lee

Nicholas Kucharewski, Jr

Thomas Y Ho

Jesse H Jenkins, Iv

Derek R Curd

Sholeh Diba

Kyle Corbett

David A Harrison

Isaak Veytsman

Jeffrey Goldberg

Ahmad R Ansari

Nabeel Shirazi

Kameswara K Rao

Sonal Santan

Schuyler E Shimanek

Adam P Donlin

Sabyasachi Das

Shay Ping Seng

Amit Kasat

Wei-Yi Ku

Tomai Knopp

Sanford L Helton

Kam-Wing Li

Frank C Wirtz, Ii

John R Hubbard

Christopher J Case

Srinivas Beeravolu

Hua Xue

Umang Parekh

Carol A Fields

Anthony D Williams

Dhimant Patel

Biping Wu

Veena N Kumar

Roberta E Fulton

The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

Automated pipeline insertion on a bus

System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

Interface firewall for an integrated circuit of an expansion card

Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

System level circuit design

A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Deadlock-resistant bus bridge with pipeline-restricted address ranges

Integrated circuits are disclosed that have interconnected programmable logic, and configuration memory. The interconnected programmable logic is connected by a logical interconnection network. The integrated circuits have a configurable function unit including a function unit component, such as a counter or shift register. The integrated circuits further include a configurable decoder, which decodes a value presented by the function unit component based on decoder configuration data. The integrated circuits also have at least one decoder output, which provides information about a comparison of the decoder configuration data with the value presented by the function unit component.

Embedded function units with decoding

A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.

Clock enable control circuit for flip flops

A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed. No specific input/output pins are required; in fact, no external connections are required at all, though one or more may be used as inputs to the control function block logic. In some embodiments, power management can be accomplished using internal, on-chip signals alone. The pin-locking capabilities (compatibility) of conventional PLD designs are not affected and all function blocks remain identical, preserving maximum design flexibility for users.

Method of minimizing power use in programmable logic devices

The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.

Method and system for HDL global signal simulation and verification

An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for simultaneous product term exporting to both previous and subsequent macrocells.

Product term exporting mechanism and method improvement in an EPLD

An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.

Structure and method for arithmetic function implementation in an EPLD

A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Circuit for partially reprogramming an operational programmable logic

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

Macrocell with product-term cascade and improved flip flop utilization

A macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device. The macrocell allows a variable number of product terms to be retained by the macrocell, and a variable number of product terms to be exported to a second macrocell. The direction in which the product terms are exported can be controlled. The macrocell further allows a variable number of product terms to be received from a third macrocell and routed either to the output terminal of the first macrocell or to the second macrocell in combination with those product terms exported from the first macrocell. Methods for routing product terms using macrocells within a programmable logic device are also provided.

High speed product term allocation structure supporting logic iteration

An input block for PLDs programmable logic devices) has a flip-flop including a master latch and a slave latch, a pad for inputting data, configuration bits, and a global clock input signal for clocking the input data to the flip-flop means. The flip-flop is controlled by the configuration bits so as to function alternatively as a register, a latch or transparently. The input block further includes at least one clock enable signal input terminal and logic elements responding to the configuration bits for providing the clock enable signal for the register function as well as the latch function of the flip-flop.

Growing community of inventors

Los Gatos, CA, United States of America

Jeffrey H Seltzer