International Business Machines Corporation

Jeffrey H Oppold

David James Hathaway

Eric A Foreman

Peter Anton Habitz

Randy William Mann

Jerry D Hayes

Anthony D Polson

Kerry Bernstein

Michael Richard Ouellette

Matthew Joseph Breitwisch

Stephen Victor Kosonocky

Jeffrey Scott Brown

John Anthony Bracchitta

Larry Wissell

A method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-based NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.

Method and structure for screening NFET-to-PFET device performance offsets within a CMOS process

A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

Slack sensitivity to parameter variation based timing analysis

A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a 'don't care' state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

Redundancy register architecture for soft-error tolerance and methods of making the same

An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.

Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits

A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

Method and design for measuring SRAM array leakage macro (ALM)

A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.

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Richmond, VT, United States of America

Jeffrey H Oppold