Adobe, Inc.

Xerox Corporation

Sun Microsystems, Inc.

Oms, Inc.

Jeffrey H Hoel

Joel B Sacks

Paul D Gettner

Pradeep S Sindhu

Richard Maurice Barth

Michel P Cekleov

Jacobo Valdes

Eduardo D Martinez

A method and apparatus for generating a compressed representation of a two-dimensional image where the image is described as a sequence of pixels in raster order. The method includes receiving the two-dimensional image as a sequence of pixels in raster order. For each pixel, the system determines whether the pixel is part of a first string of pixels that is identical to a second string of pixels found previously in the image at one of a plurality of preselected fixed distances from the first string of pixels. If so, the first string of pixels is encoded as a string token that is a reference to the second string of pixels. Otherwise, the pixel is encoded as a non-string token.

Reducing storage requirements for display data

Sets of pixel data defining parts of rasterized portions of an image are received. At least one of the parts of one of the rasterized portions of the image overlaps another part of that portion of the image. The pixel data that defines the overlapping part includes mask data that identifies pixels of the overlapping part that are to be included in the image. The sets of pixel data are decompressed. The decompressed data are used to generate a series of the rasterized portions of the image including the pixels identified in the mask data. While each of the rasterized portions of the image is being used by a print engine, another of the rasterized portions of the series is being generated.

Compositing pages from page components

Method and apparatus for reducing storage requirements for display data

A rendering device for converting input information into a bit map including a Bezier subdivision processor responsive to Bezier curve information describing a Bezier curve of an image. The Bezier subdivision processor performs at least one subdivision on the Bezier curve if the Bezier curve is greater than a desired resolution of a bit map to produce subdivided Bezier curves until all subdivided Bezier curves are at about the resolution of the bit map. The Bezier subdivision processor produces cross information from each Bezier curve which makes one crossing of a grid having the resolution of the bit map. The rendering device also includes a digital processor responsive to the cross information and operative to produce a bit map of the image from the cross information. A method for producing cross positions of Bezier curves with a grid of the present invention includes receiving a Bezier curve, sequentially subdividing the Bezier curve into a plurality of subdivided Bezier curves until each Bezier curve crosses less than a plurality of times with cell boundaries of a grid of a desired resolution, and developing the Cartesian coordinates and direction of each of the crosses of a Bezier curve with a boundary.

Memory having both stack and queue operation

A memory construct including a stack which is capable of holding one or more data items of a type and which operates as a LIFO memory, and a queue which is capable of holding one or more data items of the same type until they are used. The queue operates as a FIFO memory associated with the stack so that when the stack is empty, data is read from the queue and when the stack is not empty, data is read from the stack.

Memory construct using a LIFO stack and a FIFO queue

Method and apparatus for generating bitmaps from outlines containing

The bus of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. In a first embodiment, a high speed clock signal and slower speed clock enable signal are globally distributed from a central arbiter to agents coupled to the bus. A sending agent utilizes the high speed clock signal for source synchronized data transfers by forwarding the high speed clock signal, along with the data, to one or more receiving agents. Thus, the globally distributed clock signal is used to accomplish source synchronized data transfers. Arbitration requests, by contrast, are processed at the slower clock enable signal rate in a globally synchronous fashion. In addition, by communicating data cycles information from the central arbiter to the receiving agent at the slower clock enable signal rate, the present invention avoids resynchronization and the possibility of metastability. Dead time between packets of data is minimized in the present invention by placing the central arbiter in the center of the bus. An alternative embodiment is disclosed wherein a slower speed clock signal is globally distributed to a plurality of agents and a central arbiter. Each agent then generates a high speed clock signal that is divided down and phase locked to the slower speed clock signal, and this high speed clock signal is then utilized for high-speed, source synchronized data transfers. Arbitration and consistency information are handled at the slower speed clock signal rate. In the alternative embodiment, resynchronization is avoided through the use of a header signal.

Source synchronized metastable free bus

Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a launder is followed by a flag reset invalidating the entries in the address set. Also, the command indicates which of the valid flags should be reset. In demapping, only the flags making an entry inaccessible to the cache's processor are reset. The entries in the address set are selected based on two numbers which together provide a base three number. Each base three digit of this number specifies whether the corresponding real address bit of the entry will match if it is one or zero or 'don't care'. This permits housekeeping on any consecutive range of N addresses by specifying no more than 2 log.sub.2 N address sets which exactly cover that range. A processor initiates housekeeping by causing its cache to send a command indicating the operations to be performed and the numbers selecting the address set. In response, all caches pull down a line indicating housekeeping in progress, and that line remains down until the last cache has completed housekeeping, at which time the initiating processor is freed. Meanwhile, however, each of the caches interrupts housekeeping if it receives a command, so that non-housekeeping functions are not delayed by housekeeping. For this purpose, the execution of a housekeeping command is divided into incremental write back and flag reset operations after each of which the cache tests whether it has received a command. If not, housekeeping continues with the next write back or flag reset operation.

Multiprocessor cache memory housekeeping

Disclosed is a page printing system which uses virtual (logical) memory for mapping images. Physical memory which is used for creating a page image bitmap for synthetic graphics is to be allocated as patches. A path in general corresponds to a rectangular area of a page when the page exists in bitmap form. Each patch is represented by a set of non-contiguous segments of logical memory which, when mapped to physical memory, are contiguous.

Growing community of inventors

Palo Alto, CA, United States of America

Jeffrey H Hoel