Intel Corporation

Jeffrey G Wiedemeier

Robert Valentine

Bret L Toll

Milind Baburao Girkar

Jonathan Cannon Hall

Mark Jay Charney

Andrew Thomas Forsyth

Sridhar Samudrala

Elmoustapha Ould-Ahmed-Vall

Jesus Corbal

Edward Thomas Grochowski

Robert Dale Cavin

Dennis Ryan Bradford

Suleyman Sair

Seth Abraham

Charles R Yount

Jesus Corbal San Adrian

James Charles Abel

Lisa K Wu

Santiago Galan Duran

Roger Espasa Sans

Christopher J Hughes

Gilbert A Neiger

Jason W Brandt

Martin Guy Dixon

Srinivas Chennupaty

Rajesh S Parthasarathy

Chris J Newburn

Mark J Buxton

Peter Lachner

Mayank Bomb

Hideki (Saito) Ido

Yen-Kuang (y K) Chen

Vedvyas Shanbhogue

Arvind Raman

Krishnakumar Ganapathy

Yen-Kuang Chen

Jonathan D Combs

James D Allen

Hideki Ido

Kameswar Subramaniam

Jeff Huxel

Mark Charney

Robert C Valentine

A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

Software visible and controllable lock-stepping with configurable logical processor granularities

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Gathering and scattering multiple data elements

Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

Instruction and logic to provide vector blend and permute functionality

A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Context control and parameter passing within microcode based instruction routines

A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

Vector conflict instructions

Growing community of inventors

Austin, TX, United States of America

Jeffrey G Wiedemeier