Analog Devices,inc.

Picturetel Corporation

Polycom, Inc.

Sifly Aviation, Inc.

2wire, Inc.

Sync Computing Corp.

Analog Devices Global

Jeffrey G Bernstein

Benjamin Vigoda

Eric G Nestler

Alexander Alexeyev

William Bradley

David C Reynolds

Gary Joseph Sullivan

Robert W Adams

Brian L Hinman

Mikael Mortensen

Stephen C Botzko

Vladimir Zlatkovic

Sefa Demirtas

Jeffrey Venuti

Brian A Howell

Elizabeth M Comstock

William L Kruger

Robert V Seiler

Bernd Girod

Suraj Deepak Bramhavar

Jeffrey Chou

J Brian Harrington

Xiancheng Yuan

Benjamin Janes Beck

Titash Rakshit

Richard L Baker

Edmund S Thompson

Tony Joseph Akl

Martin McCormick

David MacDonald Hossack

David Jordan Lindbergh

Erica Lin

Muhammad Mubeen Javaid

Kartik Nanda

Theophane Weber

Andrew Schweitzer

Jason D King

Shawn Hershey

Timothy J Caputo

Rishi Chaturvedi

William Peet

Mitra M Osqui

A system including digital oscillators and at least one programmable interconnect is described. The programmable interconnect(s) provide weights for and selectably couples at least a portion of the digital oscillators. The digital oscillators and the programmable interconnect(s) form an optimization processing unit (OPU). A system for performing reversible logic is also described. The system includes digital oscillators coupled to perform a logic operation and an error correction unit coupled to the digital oscillators. The error correction unit is configured to sample states of the digital oscillators, detect error(s) in the states, and tune connection coefficient(s) between the oscillators in response to detecting the error(s).

Optimization processing unit utilizing digital oscillators

A method of assigning processing resources is described. The method includes receiving an application and analyzing the application to determine an expected run time use of the processing resources. At least a portion of the processing resources are assigned to the application based on the expected run time use of the processing resources. A computing system architecture including a processing resource pool, an interface, and a special purpose optimization coprocessor is also described. The interface receives an application to be executed. The special purpose optimization coprocessor receives information about the application and the processing resource pool and outputs an allocation scheme for allocating tasks of the application to the processing resource pool.

Real time scheduling using expected application resource usage

A method of operating an electrically powered rotorcraft of the type having a fuselage and a set of N rotors driven by a set of electric motors and coupled to the fuselage, N≥4, under a failure condition preventing ordinary operation of the rotorcraft. The method includes entering a failsafe mode of operation wherein autorotation of at least four of the rotors is enabled. The method also includes using electrical braking associated with a selected group of the rotors to control pitch, roll and yaw of the rotorcraft.

Rotorcraft autorotation control through electrical braking

An improved vertical takeoff aircraft of the type having a set of pads that are in contact with the ground when the aircraft is at rest on the ground and a controllable lift and propulsion system. The aircraft includes an array of force sensors coupled to the set of pads. The array has an output providing measurements over time of forces exerted on the pads along at least two independent axes. The aircraft also includes a controller, coupled to the lift and propulsion system and to the array of force sensors. The controller is configured to control the lift and propulsion system in a manner to counteract forces exerted externally on the aircraft that would cause undesired motion of the aircraft when on the ground and transitioning from the ground to flight.

VTOL take-off control system

A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Systems and methods for ultrasound beamforming

A method of operating an electrically powered rotorcraft of the type having a fuselage and a set of N rotors driven by a set of electric motors and coupled to the fuselage, N&#x2265;4, under a failure condition preventing ordinary operation of the rotorcraft. The method includes entering a failsafe mode of operation wherein autorotation of at least four of the rotors is enabled. The method also includes using electrical braking associated with a selected group of the rotors to control yaw of the rotorcraft.

Electrically powered rotorcraft capable of autorotative landing

Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

Convolutional neural network

Activity monitors and smart watches utilizing optical measurements are becoming widely popular, and users expect to get an increasingly accurate estimate of their heart rate (HR) from these devices. These devices are equipped with a light source and an optical sensor which enable estimation of HR using a technique called photoplethysmography (PPG). One of the main challenges of HR estimation using PPG is the coupling of motion into the optical PPG signal when the user is moving randomly or exercising. The present disclosure describes a computationally feasible and fast HR estimation algorithm to be executed at instances of little or no motion. Resulting HR readings may be useful on their own, or be provided to systems that monitor HR continuously to prevent the problem of such systems being locked on an incorrect HR for long periods of time. Implementing techniques described herein leads to more accurate HR measurements.

On-demand heart rate estimation based on optical measurements

Heart rate monitors are plagued by noisy photoplethysmography (PPG) data, which makes it difficult for the monitors to output a consistently accurate heart rate reading. Noise is often caused by motion. Using known methods for processing accelerometer readings that measure movement to filter out some of this noise may help, but not always. The present disclosure describes an improved front-end technique (time-domain interference removal) based on using adaptive linear prediction on accelerometer data to generate filters for filtering the PPG signal prior to tracking the frequency of the heartbeat (heart rate). The present disclosure also describes an improved back-end technique based on steering the frequency of a resonant filter in order to track the heartbeat. Implementing one or both of these techniques leads to more accurate heart rate measurements.

Time-domain interference removal for heart rate measurements

Tracking mechanism for heart rate measurements

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Datapath circuit for digital signal processors

An inference task is performed using a computation device having a plurality of processing elements operable in parallel and connected via a connectivity system. Performing the task includes accepting at the device a specification of at least part of the inference task. The specification characterizes a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. Each of the processing elements is configured with data defining one or more of the plurality of factors. At each of the processing elements, computation associated with one of the factors is performed concurrently with other of the processing elements performing computation associated with different ones of the factors. Messages are exchanged via a connectivity system. The messages provide inputs and/or outputs to the processing elements for the computations associated with the factors and provide a result of performing of the at least the part of the inference task.

Programmable probability processing

In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.

A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Storage devices with soft processing

Growing community of inventors

Middleton, MA, United States of America

Jeffrey G Bernstein