Altera Corporation

Jeffrey Fox

Craig S Lytle

Philip Andrew Simpson

Brad Kadet

Roger Bryner

Michael David Hutton

Chuck Rumbolt

Philippe Molson

Tony San

Jakob Raymond Jones

Ziad M Abu-Lebdeh

Kevin W Mai

Yury Markovskiy

Herman Henry Schmidt

Nikolaos Liveris

Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be synchronized with a reference clock signal at a rate determined by the relationship between the reference clock signal and the variable frequency oscillator signal. A parameter may indicate a target range for the deviation between the two signals and a runtime monitor may be used together with the parameter setting to decide whether synchronization is required and make the appropriate adjustments.

Parameterizable method for simulating PLL behavior

A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment.

Methods and tools for designing integrated circuits with auto-pipelining capabilities

Partially opaque intellectual property (IP) includes source code providing the IP functionality. Meta-comments (pragmas or attributes) are provided with the source code to enable visibility of one or more nodes in the IP. Aliasing of the visibility-enabled nodes may also be provided for using meta-comments in the IP source code. The visibility-enabled nodes may be used by system designers in debugging a system design in either a software simulation environment and/or in debugging of a hardware device implementing the partially opaque IP.

Debuggable opaque IP

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, systems, apparatus, methods and computer program products control use of hardware and software and IP implemented as user logic in a programmed device. The programmed device includes programmed logic that has designed logic and control logic. The designed logic includes user logic and protected logic such as IP cores, the use of which is to be controlled. The control logic includes a signal generator external to the designed logic. This signal generator contains clock means and a timeout circuit. A controller is connected to the programmed device by a tether. The controller periodically sends a keep alive signal via the tether to the signal generator. These keep alive signals may be single bit or multi-bit tokens which are processed in the programmed device by the signal generator. The signal generator disables the programmed device when the signal generator reaches a programmed time limit before receiving a keep alive signal from the controller. Disabling the programmed device can be accomplished by disabling either the user logic or the protected logic or both.

Method and apparatus for controlling evaluation of protected intellectual property in hardware

Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a 'system level netlist.' This system level netlist contains 'system level instances' corresponding to &#x201c;hardware cells&#x201d; of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.

System level simulation models for hardware modules

A computer-system bus switch architecture is presented that has high throughput and low latency. The architecture provides a multi-port PCI bus switch that includes a primary port controller, a crossbar switch, and a plurality of secondary port controllers. The primary port controller couples to a main system bus to which, for example, a system controller is coupled, and the secondary port controllers are each coupled to a local bus to which a plurality of peripheral devices are coupled. The crossbar switch selectively routes traffic from any port controller to any other port controller.

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Los Gatos, CA, United States of America

Jeffrey Fox