Bae Systems Information and Electronic Systems Integration Inc.

Jeffrey E Robertson

Dale A Rickard

Elizabeth J Williams

Mary T Hanley

Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.

Verification process for bit spreading error resistant memory system

A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Software integration into hardware verification

An apparatus for managing data queues is disclosed. The apparatus includes at least one sensor for collecting data, a data interface for receiving data from the sensor(s) and for placing the collected data in a set of data queues, and a priority sieve for organizing the set of data queues according to data priority of a specific task. The priority sieve includes a scoreboard for identifying queue priority and a system timer for synchronization.

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Ashubrn, VA, United States of America

Jeffrey E Robertson