Texas Instruments Corporation

Hitachi, Ltd.

Other

Jeffrey E Koelling

Goro Kitsukawa

Takesada Akiba

William R McKee

Hiroshi Otori

Troy H Herndon

Hugh Pryor McAdams

Albert Shih

J Patrick Kawamura

Masayuki M Nakamura

Wah Kit Loh

Ching-yuh Tsay

Paulette Thurston

Yung-Che Shih

Hugh P Mcadams

Patrick J Kawamura

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

System with meshed power and signal buses on cell array

A circuit is designed with a first transistor ( ) having a current path coupled between a supply terminal ( ) and a first output terminal ( ). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit ( ) has first ( ) and second ( ) input terminals and a second output terminal ( ). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit ( ) receives the control signal and produces an output voltage at the supply terminal.

Level detection by voltage addition/subtraction

A circuit is designed with a first transistor (,) having a current path coupled between a supply terminal (,) and a first output terminal (,). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (,) has first (,) and second (,) input terminals and a second output terminal (,). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (,) receives the control signal and produces an output voltage at the supply terminal.

A temperature dependent clock circuit (,) is disclosed. The clock circuit (,) includes a reference circuit (,) that provides a first group of reference signals (,) with positive temperature coefficients and a second group of reference signals (,) with negative temperature coefficients. A sample circuit (,) compares the first group of signals (,) with a second group of signals (,) and provides a group of bias signals (,) representative of the operating temperature of the clock circuit (,). A frequency controllable oscillator circuit (,) provides an output clock signal (CLK) having a frequency that is dependent upon the values of the bias signals (,).

On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory

A class AB amplifier (,) is disclosed, having a first input node (402), a second input node (,), and an output node (,). A push-pull input stage (412) includes cross-coupled pairs of transistors, which form a charge current path and a discharge current path. When the voltage at the first input node (,) is greater than the voltage at the second input node (,), the amount of current drawn in the charge current path increases, and the amount of current drawn in the discharge current path decreases. When the voltage at the first input node (,) is less than the voltage at the second input node (,), the amount of current in the charge current path decreases while the amount of current in the discharge path increases. A first and fourth current mirror (,and,) are coupled to the charge current path, and a second and third current mirror (,and,) are coupled to the discharge current path. In response to increases in the amount of current drawn in the charge current path, the first current mirror (,) drives a discharge node (,) to a charge voltage, and the fourth current mirror (,) drives a charge node (,) to a charge voltage. In response to increases in the amount of current drawn in the discharge current path, the second current mirror (,) drives the discharge node (,) to discharge voltage, and the third current mirror (,) drives the charge node (,) to a discharge voltage. An output driver (,) charges the output node (,) when the charge node (,) is at the charge voltage, and discharges the output node (,) when the discharge node (,) is at the discharge voltage.

Class AB amplifier for use in semiconductor memory devices

A memory circuit for operating synchronously with a system clock signal is designed with a memory array (,) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (,) produces a select signal at a respective column select line (,) in response to a first column address signal. A plurality of sense amplifier circuits (,) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (,). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (,) is coupled to receive four data bits from four respective data lines (,) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (,) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.

Synchronous dynamic random access memory with four-bit data prefetch

An architecture for a high-capacity high-speed synchronous dynamic random access memory (SRAM) (,) is disclosed. The SDRAM (,) includes memory cells logically arranged into a number of array banks (,). The array banks (,) each include first sub-banks (,) situated toward a first end of the SDRAM and second sub-banks (,) situated toward a second, opposing end of the SDRAM (,). Sub-bank buses (,), each of which includes a number of data I/O lines, couple each of the first sub-banks (,) to a first I/O circuit (,) situated toward the first end of the device, and couple each of the second sub-banks (,) to a second I/O circuit (,) situated toward the second end of the device. In this manner, overlap of the sub-bank buses (,) is limited toward the first and second ends of the device, eliminating the need to run data I/O lines across the device, and thus preventing a data I/O line routing bottleneck in the central portion of the SDRAM (,).

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Dallas, TX, United States of America

Jeffrey E Koelling