Lucent Technologies Inc.

Agere Systems Inc.

Jeffrey Devin Bude

Marco Mastrapasqua

Mark Richard Pinto

Richard Joseph McPartland

Ranbir Singh

Clifford Alan King

Malcolm Carroll

David Abusch-Magder

Kevin John O'Connor

Hong-Ih Louis Cong

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

Semiconductor devices with reduced active region defects and unique contacting schemes

A semiconductor device in which hole-induced damage to the dielectric layer is reduced is disclosed. In the device, a layer of a conductive, high bandgap (i.e. a material with a bandgap greater than 1.1 eV) material is formed adjacent to the dielectric layer. The presence of the high bandgap material reduces the hole-induced damage to the dielectric layer that occurs during device operation compared to devices in which the conductive material adjacent to the dielectric is silicon.

Semiconductor device with increased gate insulator lifetime

The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection

A method for programming and/or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices in a NOR array is disclosed. In the method, either a program verify or an erase verify is performed intermittently with the programming of a device or the erasure of the array. During the program-verify, one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to both the selected and deselected devices in the array, or both conditions are applied. Performing the program verify or erase verify in this manner is efficient and accurate. During the programming step, it is also advantageous if one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to the selected devices in the array, or both. With the application of a negative V.sub.CS to the deselected devices during programming, if there are any over-erased devices in the array, the presence of the over-erased devices will not adversely affect the programming of the devices.

Method for erasing and programming memory devices

An integrated circuit includes at least one non-volatile memory element having first and second non-volatile transistors connected in series between first and second data lines. A junction between the first and second non-volatile transistors forms an output node. The non-volatile memory element further includes an access transistor connected between a reference voltage line and the junction between the first and second non-volatile transistors. In a programmable logic application, for example a field programmable gate array, the non-volatile memory element controls the state of a switching element, which selectively connects logic elements in the programmable logic application. Based on the voltages applied to the non-volatile memory element, the non-volatile memory element is selectively erased, programmed, operated, monitored and powered-up.

Non-volatile memory element for programmable logic applications and

A process for introducing negative charge onto the floating gate of an EPROM or EEPROM device is disclosed. The process uses CHISEL conditions to introduce charge onto the floating gate. The threshold voltage of the device is controlled by selecting a control gate voltage during programming that is less than 10 volts and that will provide a device with the desired threshold voltage. The device is then programmed using the selected control gate voltage and a negative substrate bias.

Method for changing electrically programmable read-only memory devices

The invention is directed to a memory cell with a floating gate and a method for charging the floating gate using channel-initiated secondary electron injection (CISEI). In the device of the present invention, a positive bias voltage of about 1.1 volts to about 3.3 volts is applied between the drain and the source when introducing charge onto the floating gate. A negative bias voltage of about -0.5 volts or more negative is applied to the substrate and the source. The drain substrate bias induces a sufficient amount of secondary hot electrons to be formed with a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate to charge the floating gate.

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New Providence, NJ, United States of America

Jeffrey Devin Bude