Motorola Corporation

Jeffrey D Quinn

Oded Yishay

Joseph Jelemensky

Daniel W Pechonis

Data processor (10) configures internal circuitry during execution of a reset operation in response a logic state of a Mode Select signal. If an external bus control (44) determines the Mode Select signal is in a first logic state, configuration data is provided from a mask register (40). The data is transferred to a plurality of configuration registers (50) and, subsequently, to a remaining portion of data processor (10). If the Mode Select signal is in a second logic state, configuration data is provided from a plurality of bus terminals (48). The data is transferred to the plurality of configuration registers (50). The contents of the plurality of configuration registers (50) are transferred to bus interface unit (42) which subsequently transfers the data to a remaining portion of data processor (10).

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Austin, TX, United States of America

Jeffrey D Quinn