Fujitsu Corporation

Hal Computer Systems, Inc.

Jeffrey D Larson

Takeshi Horie

Takashi Miyoshi

Hirohide Sugahara

Albert Mu

Thomas M Wicki

Raghu Sastry

Richard L Schober, Jr

John R Slice

Patrick James Helland

One embodiment of the present invention provides a method for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a method for communicating request packet information from a network to a PCI environment. Another embodiment of the present invention provides a system for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a system for communicating request packet information from a network to a PCI environment.

PCI bridge over network

A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers and expected sequence numbers. The expected sequence number of a data packet corresponds to the sequence number of the data packet immediately prior to the current data packet. When a data packet arrives at the receiving bus, its expected sequence number is compared against the sequence numbers of the previous data packets received. If the previously-received data packet bears the sequence number corresponding to the expected sequence number of the newly arrived data packet, the newly arrived data is stored, and an acknowledgement is sent. If a match cannot be found then a retry request message is sent.

Simplified pipeline writes over a network

A method and system provide access assurance regarding an RDMA transaction. The system comprises an initiating device and a target device placed across a network. The initiating device and the target device are coupled to a first and a second buses, respectively. The first and the second buses are coupled to the network router through a first and a second network adaptors. An RDMA space and an associated access assurance space are assigned to the target device in the memory space of the first bus. The initiating device may RDMA the target device by directly reading from or writing into the RDMA space assigned to the target device. To obtain access assurance information regarding the RDMA transaction, the initiator performs a read from the assurance space associated with the RDMA space of the target device in the memory space of the first bus.

Access assurance for remote memory access over network

A method and apparatus for avoiding starvation at an initiator node in a computer network to which are connected at least one target node which provides service and a plurality of initiator nodes which request service from the target node. The method includes: when a request is received from the initiator node during a period that the target node is unable to provide service, returning a reject reply by attaching thereto reject time information that matches the period; when the target node is in a state capable of providing service, preferentially accepting a retry request carrying older reject time information; and when the target node is in the state capable of providing service, returning a reject reply by attaching thereto new reject time information in response to any first request received before retry requests arising from previously rejected requests are all accepted.

Method and apparatus for avoiding starvation in computer network

One embodiment of the present invention provides a method for processing a remote interrupt signal or a remote event. Another embodiment of the present invention provides a system for issuing a raw packet over a network in response to a remote interrupt or a remote event. Another embodiment of the present invention provides a network interface system configured to issue interrupt requests over a network.

Launch raw packet on remote interrupt

A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.

Fast delivery of interrupt message over network

A PCI (peripheral component interconnect) network adaptor manages read/write requests through the establishment of dynamic queues. The PCI network adaptor establishes a unique queue for each destination node that enables the requests for each node to be processed separately. The PCI network adaptor determines whether a remote read/write request should be added to the linked list for the destination node of the request or whether the request should be rejected. If the number of pending requests for the destination node is below a predetermined threshold and the entire buffer is not full, then the request is added to the linked list for the destination node. Otherwise, the request is rejected. For write requests, if the request is added to the linked list for the destination node, then any pending read requests for that node are aborted.

Dynamic queuing for read/write requests

A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system includes at least one crosspoint circuit. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. A method for transferring data using a crosspoint circuit includes a charging first voltage line and a second voltage line to a predetermined voltage level, discharging the predetermined voltage level in the first voltage line, maintaining the predetermined voltage level in the second voltage line concurrently with the discharging step, receiving a high clock signal at a sense amplifier, and generating an output signal based on a differential voltage level at the arrival of the clock signal.

Crossbar switch and method with crosspoint circuit

A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.

System and method for controlling data transmission between network

A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. The method of the unit comprises the steps of charging a first and a second reduced voltage swing line to a predetermined voltage, discharging the voltage from the first reduced voltage swing line, maintaining the voltage in the second voltage line, receiving a clock signal at the sense amplifier, and generating an output signal based on a voltage differential between the voltage lines.

Crossbar switch and method with reduced voltage swing and no internal

A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any 'stuck at' or 'open' faults in the link.

Interconnect fault detection and localization method and apparatus

Arbitration apparatus and method coordinate access to an output of a routing device in a packet switching network. Access to the output is granted to requests having the highest priority in a current arbitration cycle. For requests having the same priority, access is granted to the first of such requests received. Before granting a request, the arbitration apparatus ensures a receiving input buffer has sufficient space for a data packet, as well as any higher priority traffic.

Method and apparatus for coordinating access to an output of a routing

An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.

Low latency, high clock frequency plesioasynchronous packet-based

A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the relationship between a delayed data phase signal driven by a non-delayed source domain clock and a data phase signal sampled by a delayed receiving domain clock. The result of the comparison determines along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. An XNOR comparator responds to the relationship between a delayed data phase signal driven by a non-delayed source domain clock and a data phase signal sampled by a delayed receiving domain clock to determine which one of the multiple data paths transfers the data frame.

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San Jose, CA, United States of America

Jeffrey D Larson