International Business Machines Corporation

Jeffrey D Gilbert

Arne Watson Ballantine

Glenn Robert Miller

Douglas Duane Coolbaugh

Glen L Miles

James J Quinlivan

Kevin K Chan

James Albert Slinkman

Edward Crandal Cooney, Iii

Ronald A Warren

Joseph R Greco

Beth A Ward

Samuel C Ramac

Michael B Rice

Kevin M Houlihan

John J Ellis-Monaghan

Toshihura Furukawa

Amy L Myrick

Robert G Miller

Anthony K Stamper

James William Adkisson

Kirk David Peterson

Andrew Herbert Simon

Stephen Edward Greco

Jeffrey Scott Brown

Stephen Peter Ayotte

Nancy Anne Greco

Peter John Geiss

Timothy M Sullivan

Shwu-Jen Jeng

Ronald Dean Goldblatt

Tina Jane Wagner

Ronald Lee Mendelson

Anthony C Speranza

Donna Kaye Johnson

Robb Allen Johnson

James J Toomey

George A Dunbar, Iii

David J Hill

Frank V Liucci

Matthew D Gallagher

Cheryl Faltermeier

David H Yao

Bruce A Root

Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.

Production of integrated circuit chip packages prohibiting formation of micro solder balls

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

CMOS transistor with a polysilicon gate electrode having varying grain size

A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Discontinuous dielectric interface for bipolar transistors

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

DC or AC electric field assisted anneal

A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600&deg; C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600&deg; C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface. In addition, the monitor may be reconditioned for repeated use by heating the monitor in a hydrogen ambient environment to convert the oxide layer to unoxidized copper. Additionally, the oxide layer has a color that is a function of the oxide layer thickness, where the color may be used to estimate the temperature at which the wafer was heated in the ambient oxygen atmosphere.

Metal oxide temperature monitor

A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Structure and method for formation of a blocked silicide resistor

A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.

Method for forming a liner in a trench

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Method of annealing copper metallurgy

A method of substantially reducing stress in a trench comprising forming at least one trench in a substrate, said substrate having a surface; filling the at least one trench with a trench dielectric material; planarizing the filled trench stopping on said surface of said substrate; and subjecting the planarized trench to an anneal step, said anneal step being carried out under rapid thermal conditions at a temperature of about 800&deg; C. or above and in the presence of an atmosphere comprising hydrogen.

Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield

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Burlington, VT, United States of America

Jeffrey D Gilbert