Motorola Corporation

Jeffrey D Ganger

Kenneth R Burch

Jules D Campbell, Jr

Roger A Whatley

Robert S Jones, Iii

Sangil Park

Kelvin E McCollough

Kuntal Joardar

Adrian B Early

Kenneth C Weng

Der-Gao Lin

Kevin Yun-kang Wu

Christopher Sterling Lohn

Jeff D Stump

A method of forming a stacked capacitor structure in a semiconductor device, having metal electrode plates. After depositing the bottom electrode layer (26) and the dielectric layer (28) of the capacitor, a rough patterning step is carried out to roughly pattern or shape the bottom electrode layer and the dielectric layer, and to expose the underlying interlayer dielectric (18). A top electrode layer (32) is then blanket deposited, and another, more precise etching step is carried out to form the final shape of the capacitor element, while leaving behind a portion of the top electrode layer on the interlayer dielectric, which forms a metal interconnect (36). In one embodiment, the electrode layers are comprised of materials having a conductivity greater than doped silicon (either poly or monocrystalline), such as a metal.

Method for forming a semiconductor device having a capacitor structure

A Schmitt trigger (30) operates at low power and low frequency and can be implemented in a small amount of surface area on an integrated circuit. Specifically, the Schmitt trigger (30) includes transistors (34, 40) that are implemented as long channel devices and operate in a linear region for providing resistive elements, and another pair of transistors (44, 46) that function as non-linear devices allowing a current through the Schmitt trigger (30) to provide both a reference and the switchpoints for the Schmitt trigger (30). These transistors also establish low current through the Schmitt trigger (30).

Low power schmitt trigger

A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

Circuit die having improved substrate noise isolation

Compensation for a second pole located at an internal node (107 and 108) of a two pole cascode differential amplifier (30) is accomplished by introducing a left half plane zero in the transfer function of the cascode differential amplifier (30). This is done by coupling a compensation capacitor (46, 47) between an output node (105, 106) and the internal node (107, 108) of the cascode differential amplifier (30). The compensation capacitors (46, 47) improve high frequency performance of the amplifier (30) by improving phase margin and increasing stability.

Pole/zero compensation in cascode amplifiers

A fully differential switched-capacitor biquad low pass filter (40) includes a first stage (54), second stage (56), common-mode circuits (55, 72), and feedback transmission gates (73, 74). The first stage (54) includes a first operational amplifier (47), and the second stage (56) includes a second operational amplifier (69). Glitches, or transients, which are caused by the operational amplifiers (47, 69) operating in slew rate limit mode, are prevented from affecting the differential output signals of the filter (40) when the filter (40) is operating with a continuous time output. This is accomplished by preventing the operational amplifiers (47, 69) from operating in slew rate limit mode, or by adjusting the clock signals such that the output of the filter (40) is not coupled to an operational amplifier (47, 69) that is recovering from operation in slew rate limit mode.

Glitchless switched-capacitor biquad low pass filter

A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Charge-balanced switched-capacitor circuit and amplifier circuit using

A slew rate limited output driver circuit has an output terminal which varies between two power supply voltage levels in response to an input data signal. The output signal is slew rate limited by a capacitor. In order to prevent a full range of the output voltage from being placed across the capacitor, the voltage across the capacitor is limited to only one-half the full range by forcing one electrode of the capacitor to remain at a voltage potential equal to a reference voltage which, in one form, is substantially halfway between the two power supply voltages.

Low power output driver circuit with slew rate limiting

An input protection circuit is provided which prevents positive and negative voltages significantly higher than a supply voltage potential from damaging operational circuitry connected to an input terminal. A bipolar transistor has current conducting electrodes connected between the supply voltage and the input terminal. A first MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and collector of the bipolar transistor in response to the sign and magnitude of an input signal. A second MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and emitter of the bipolar transistor in responses to the sign and magnitude of the input signal.

Semiconductor protection circuit having both positive and negative high

A driver circuit which provides an output voltage which is slew rate limited substantially independent of the value of any load which may be coupled thereto is provided. A pair of transistors of opposite conductivity type operate in push-pull fashion to drive the output voltage in response to a control signal. Capacitors are utilized to perform slew rate limiting. Additionally, each of the transistors is selectively dynamically biased to insure a substantially linear slew rate.

Growing community of inventors

Austin, TX, United States of America

Jeffrey D Ganger