Credence Systems Corporation

Jeffrey D Currin

Henry Y Pun

Philip Theodore Kuglin

Douglas J Chapman

Michael R Ferland

Kenneth L Skala

James Michael Jula

Jacob Herbold

Manohari Reddy

D James Chapman

Vicki L Skala, Legal Representative

Mark Dahl

An efficient automated test system and method are presented. In one embodiment, an automated test system is implemented in a routed event distribution architecture. In one exemplary implementation, an automated test system includes a plurality of test instruments, a switched event bus, and a test controller component. The plurality of test instruments perform testing. The switched event bus communicatively couples the plurality of instruments. The switched event bus comprises an event distribution switch that flexibly routes event information across event lines of the switched event bus. The test controller controls the testing and the switched event bus.

Routed event test system and method

A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals (&ldquo;beat&rdquo; and &ldquo;clock&rdquo;) wherein the period P,of the beat signal and the period P,of the clock signal are related by the expression P,&equals;P,(N&plus;1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.

System for linearizing a programmable delay circuit

In an integrated circuit tester module, pin electronics circuitry supplies leakage current to a circuit node which is connected to a signal pin of a device under test. The leakage current is compensated by connecting the circuit node to a voltage source at a first potential level, supplying current to the circuit node from a second potential level, and measuring current supplied to the circuit node from the voltage source. The second potential level is selectively varied in a manner such as to reduce the current supplied from the voltage source substantially to zero. The circuit node is then disconnected from the voltage source.

Integrated circuit tester with compensation for leakage current

A programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A programmable data converter converts input data indicting a desired phase shift between the reference signal and the output signal into data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The relationship between conversion table input and output data is adjusted so that the period of the output signal has a desired linear relationship to the input data value.

Calibratable programmable phase shifter

Current consumption of a device under test (DUT) is measured using a tester including a device power supply (DPS) having force and return lines terminating in respective power supply terminals. The DUT is removably received by a load board having contact elements which are in electrically conductive pressure contact with the power supply terminals of the force and return lines and are connected to power supply pins of the DUT. A circuit branch including a bypass capacitor and an nMOSFET is connected between the force and return lines.

Integrated circuit tester with test head including regulating capacitor

A circuit tester stimulates an analog circuit device under test (DUT) with a test signal and periodically digitizes a resulting DUT output signal to produce an output data sequence that may be analyzed to ascertain DUT operating characteristics. The tester is powered by a switching power supply that induces periodic noise spikes in the DUT output signal. To eliminate the influence of the noise spikes on test results, the period of the switching power supply noise is made coherent with the digitization period. The phase of digitization is then adjusted so that the tester avoids digitizing the noise spikes in the DUT output signal.

Coherent switching power for an analog circuit tester

A timing signal generator adjustably times successive pulses of an output timing signal. The generator receives input data before each output pulse and controls the timing of that output pulse in accordance with the input data. The generator includes a circuit providing a set of 2N phase signals frequency locked to a reference clock signal but evenly distributed in phase. First and second selectors each sample the data once during each cycle of the clock signal. The sampled data tells the first selector whether it is to produce a first output signal during the next clock signal cycle and, if so, which of the first N phase signals the first selector is to select for controlling timing of edges of the first output signal. The sampled data also tells the second selector whether it is to produce a second output signal during a next clock signal cycle and, if so, which of the second N phase signals the second selector is to select for controlling the second output signal. The first and second output signals are logically ORed to produce the timing signal. The timing of data sampling by each selector is separately adjusted so that the selector output signal changes state only when the selected phase signal changes state and not when the selector changes its selection in response to newly sampled input data.

Apparatus for controlling timing of signal pulses

A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.

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Pleasanton, CA, United States of America

Jeffrey D Currin