Texas Instruments Corporation

Jeffrey D Bellay

Kevin C McDonough

John W Hayn

Robert C Thaden

Theo J Powell

Michael W Patrick

Gary L Swoboda

Martin D Daniels

Yin-Chao Hwang

Stanley M Dennison

John W Mayn

Michael J Hogan

A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all macrocode bits is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to address all bytes of macrocode and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.

Microcomputer with self-test of macrocode

A sense amplifier for a read only memory cell array which includes a dynamic NOR circuit having high impedance inputs coupled to bitlines of the array. An inverter circuit has an input coupled to an output of the dynamic NOR circuit. An output buffer circuit has an input coupled to an output of the inverter circuit.

Sense amplifier for a read only memory cell array

A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.

Parallel/serial scan system for testing logic circuits

A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.

Partitioned scan-testing system

A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. In the normal single-chip operation mode, a macrocode word is fethched from on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. In another mode, such as used for self-test employing a check-code, the device loads macrocode from external into on-chip RAM then executes from RAM to perform the desired routine, switching modes of operation.

Microcomputer with internal selection of on-chip or off-chip access

An electrically programmable read-only memory including a memory array of several bits capable of storing binary data connected to an address circuit for accepting a plurality of bits that designate a selected set of the memory array bits and further connected to a data latch to store data to be programmed in a selected set of memory bits. Further provided is a high voltage circuit for providing a high voltage to the selected set of bits according to the data in the data latch and for programming the data in the selected set of memory array bits. Further provided is an output circuit to provide a precharge signal to the memory array bits and to output data programmed in a selected set of memory array bits designated by the address circuit.

Precharged discharge sensing for EPROM

The present invention is an emulator device for emulation of the functions and operation of a predetermined semiconductor device. A central portion of a semiconductor substrate of the emulator embodies the emulated semiconductor device. This embodiment of the emulated semiconductor device is an exact replica of the emulated device including all input and output connections. The emulator device further includes an additional set of input/output connections located on the periphery of the substrate outside the central portion. These additional input/output connections are connected to portions of the emulated device in the central portion of the substrate. These connections permit additional input signals to be coupled to the emulated device and additional output signals to be received from the device to enable greater control over and monitoring of the emulated device. This periphery preferably also includes further circuits for use in the emulator device for signal conditioning and the like. The preferred embodiment of the emulator further includes an external memory not formed on the same substrate which can be substituted for a similar memory within the emulated device. By this procedure, a program may be tested and debugged prior to embodiment within the emulated device.

Emulator device including a semiconductor substrate having the emulated

A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all microcode bits, or all macrocode and microcode bits, is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to access all bytes of microcode (or both microcode and macrocode) and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.

Microcomputer with self-test of microcode

A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.

Microcomputer with automatic refresh of on-chip dynamic RAM transparent

An electronic digital processor system including an internal memory for the storage of data and commands, an arithmetic and logic unit, a register set, data paths and control/timing circuitry together with peripheral control circuitry which provides a number of memory configurations and also provides offset addressing capability to access the interrupt control circuitry, interval timing circuitry and input/output ports. The several memory configurations include configurations that allow for the storage of commands and the storage of data in external devices interfaced to the processor system through the input/output port circuitries.

Digital processor or microcomputer using peripheral control circuitry to

An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the internal mode, the data and the commands are stored in the internal memory. In the external mode, the commands which control the operations of the microcomputer are stored in the external memory. In the emulator mode, the user can combine the microcomputer with external devices to emulate a composite system with minimal hardware. The emulator mode would also allow the user to develop software for the composite system.

Self-emulator microcomputer

A electronic digital processor system input/output circuitry including several input/output data ports where each port contains receiving circuitry to receive bit data from bit data pads and transmitting circuitry to transmit bit data to the data bit pads and control circuitry that provides for a configuration where one input/output port may respond to the address of another input/output port, allowing the second input/output port to perform other functions. This capability would allow a user to execute a program that emulates one configuration while the actual, physical connection of devices is, in fact, another configurations. The input/output circuitry also include control circuitry that determines whether the port is to receive bit data or to transmit bit data. This circuitry is connected to a data bus that couples the input/output data ports to the remaining electronic digital processor system.

Multiprogrammable input/output circuitry

A microcomputer device is disclosed containing a read-only memory for programs, a read/write memory usually containing data, and a CPU, all in a single integrated circuit. The CPU is microprogrammed in that each instruction word fetched from the program memory initiates a sequence of microinstructions to perform the operation defined by the instruction word. The sequence is determined by addresses for a control ROM, and the addresses are selected by a method referred to as dispatching. The control ROM output includes a jump address by which the next address may be any location in the entire control ROM address range. Alternatively, the jump address may be modified by any one of several dispatches. A group dispatch selects one of the modes of accessing source and/or destination operands, based on one field of the instruction word. A subsequent function dispatch selects one of the set of available arithmetic/logic operations to be performed in the CPU based on another field of the instruction word. Many of the microinstructions are shared by the various sequences; the opcode stays in the instruction register so it can be used for dispatch control even after many microinstruction states have been executed.

Growing community of inventors

Houston, TX, United States of America

Jeffrey D Bellay