Analog Devices,inc.

Mediatek Singapore Pte. Ltd.

Jeffrey Carl Gealow

Michael Anthony Ashburn, Jr

Thomas James Barber, Jr

Paul F Ferguson

José Barreiro Da Silva

Patrick Stanley Riehl

Paul F Ferguson, Jr

Palle Birk

Joern Soerensen

Anthony L Kelly

Stacy Ho

Xavier S Haurie

Michael A Ashburn

An automatic gain control circuit includes an input gain stage for receiving and amplifying an analog input signal; an analog-to-digital converter for receiving the amplified analog input signal and providing a digital output signal; and an overload management module. The overload management module is arranged to receive the digital output signal; determine therefrom whether the received, amplified analog input signal exceeds an operating range of the analog-to-digital converter; and provide a first control signal to the input gain stage to adjust a gain of the input gain stage in response thereto.

Analog-to-digital converter circuit, integrated circuit, electronic device and method therefor

A circuit for calibrating selective coefficients of a delta-sigma modulator is provided. The circuit includes a calibration logic module that is coupled to one of a plurality of stages of the delta-sigma modulator. The calibration logic module measures the oscillating frequency of a respective stage and compares it to a reference frequency. The calibration logic adjusts a selective circuit component associated with the respective stage so that the reference frequency and the oscillating frequency match.

Calibration of time constants in a continuous-time delta-sigma converter

An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Continuous-time oversampled converter having enhanced immunity to noise

A continuous-time sigma-delta analog-to-digital converter includes a first integrator stage to integrate a difference between a first differential signal derived from a differential analog input signal and a second differential signal derived from a quantized output signal, a quantizer and a low pass filter. The first integrator stage has a differential operational amplifier, first, second, third, and fourth input resistors, and a first pair of integrating capacitors. The differential analog input signal is received at first and second input nodes of the converter. The first and third input resistors are coupled in series between the first input node and a first input of the operational amplifier. The second and fourth input resistors are coupled in series between the second input node and a second input of the operational amplifier. The first and second input resistors are coupled to the third and fourth input resistors, respectively.

Continuous-time oversampled converter having passive filter

A dual-mode delta-sigma analog to digital converter system is disclosed that uses a feed forward modulator and includes a low frequency resonator circuit and a high frequency resonator circuit and includes a feed-forward path from the final integrator in the high-frequency resonator circuit to a summer. The digital converter system includes a selection unit for permitting the high frequency resonator circuit and the low frequency resonator circuit to be employed in a first mode of operation. The system also permits the high frequency resonator circuit and the feed-forward path from the final integrator in the high-frequency resonator circuit to the summer to be disabled in a second mode of operation.

Dual-mode delta-sigma analog to digital converter system and method

A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Clock enable system

A sample rate conversion system developed to implement a rate change of M/N using a very efficient design implementation. The sample rate conversion system of the present invention is implemented as a CIC-based interpolating sample rate converter with noise-shaped control of the N value. For a decimator, noise-shaped control of the M value is utilized. In the interpolator, the N value is the correct value on average, but demonstrates instantaneous errors (&ldquo;non-uniform&rdquo; resampling) that are corrected through noise-shaping. The CIC SRC implementation capitalizes on the fact that the outputs of the CIC that are discarded during downsampling need not be calculated by the CIC in the first instance. The combination of the computational simplicity of CIC SRC with noise-shaped, non-uniform resampling performs the sample rate conversion very economically and facilitates conversion between a plethora of sample rates at the input and output without requiring the various filters to be explicitly formulated. A method for sample rate conversion is also described.

Sample rate converter with rational numerator or denominator

An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.

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Andover, MA, United States of America

Jeffrey Carl Gealow