International Business Machines Corporation

Globalfounders Inc.

Jeffrey C Stamm

Pierre J Bouchard

Howard Ted Barrett

Karen Strube Edwards

Maureen Fitzpatrick McFadden

James B Clairmont

John F Rudden, Jr

Florence Marie St Pierre Sears

Anthony K Stamper

Patrick S Spinney

A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.

Semiconductor test structure and method for forming the same

A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.

System and method of automatically generating kerf design data

Growing community of inventors

Colchester, VT, United States of America

Jeffrey C Stamm