Johnstech International Corporation

Jeffrey C Sherry

Gary William Michalko

Brian Warwick

John E Nelson

Michael W Andres

Joel N Erdman

Russell F Oberg

Patrick J Alladio

Cory Kostuchowski

David A Johnson

Brian Halvorson

Brian Eshult

John DeBauche

Dan Campion

Steve Rott

David T Skodje

Ranauld Perez

Sarosh M Patel

Mike W Andres

Jay Drescher

Joël Erdman

Dennis Wagner

Harlan Faller

John Bucher

Gary W Michalko

A high density thin walled test device testing chips/ICs is disclosed. A housing includes a slot for a contact pin and a pair of elastomers. The pin has an arcuate recess to receive part of the elastomer. Likewise the housing includes a channel to receive part of the elastomer. The recess and channel together partially surround the elastomer but not completely to allow shear forces and expansion space for the elastomer as it is compressed by the channel and recess. In addition, a front channel extends from the top surface of the housing toward the bottom surface but leaving a floor to support the elastomer so that it does not warp the housing when compressed. Further, the channel or the recess may include retainers which prevent the elastomer from moving out of position when the pin is in an uncompressed state.

Self flattening test socket with anti-bowing and elastomer retention

A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base () with apertures () for insertion of test pin insert blocks (). The blocks are inserted top&#x2014;in or bottom&#x2014;in and are provided with registration bossesand teethor other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins () from the housing.

Integrated circuit contact test apparatus with and method of construction

A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave portand a load board via a waveguide structure. The waveguide includes a wave insert, a waveguide adapterand a conductive compliant memberwhich maintains bias between the adapterand the DUT HF portwhile also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projectionwhich is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.

Waveguide integrated circuit testing

A structure and method for providing a housing which includes a high frequency (HF or RF) connection between a device under test (DUT) having a waveguide. The waveguide includes a wave insert, and a conductive compliant memberwhich maintains bias between the adapter/insertand the DUT HF portwhile also maintaining an RF shield despite the variable height of the DUT waveport. A passageprovides an RF connection between the RF porton the DUT and a RF wave guide horn. A plurality of transmitting hornscan be arranged to transmit to a single receiving hornso that fewer receivers are required to test multiple DUTs in sequence.

A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.

Integrated circuit testing for integrated circuits with antennas

The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.

Integrated circuit contactor for testing ICs and method of construction

A test socket () for a testing an integrated circuit () with controlled impedance while maintaining the structural integrity of the test pins (). The pin () can have a sidewall with a thick portionand a thinner portion () along the length of the pin. The pin can have projections () which provide a standoff from the slot (). The sidewalls themselves can have projections or lands () which extend into the slot and provide stability for the pin ().

High isolation contactor with test pin and housing for integrated circuit testing

A system and method for reducing inductance and capacitance and shielding signals in an integrated circuit test for devices under test (DUT) is disclosed. Inductance and capacitance are reduced in two ways. First, by recessing the contact pin housingdirectly into the load boardthereby eliminating much of distance between the load board and DUT. Second, surrounding the slot/wellin which each RF contact pin resides in the housing with a ground isolation cageof electrically conductive strips or rings at the top and bottom of the housing adjacent the slot with connecting vias thereby creating an isolation cage against RF cross talk transmission and further lowering inductance and capacitance.

High isolation housing for testing integrated circuits

The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.

Testing apparatus and method for microcircuit testing with conical bias pad and conductive test pin rings

The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.

Growing community of inventors

Savage, MN, United States of America

Jeffrey C Sherry