International Business Machines Corporation

Lenovo (Singapore) Pte. Ltd.

Jeffrey Buchanan Williams

Alfredo Aldereguia

Grace Ann Richter

William Bradley Schwartz

Michael Charles Elles

Marcus Alan Baker

Paul Klustaitis

Ralph Saul Cooper

Robert Anthony Fenoglio

Sumeet Kochar

Elizabeth A McGlone

Brian Thomas Vanderpool

Curtis Carl Wollbrink

Scott Neil Dunham

Edward Victor Zorek, Sr

Luis Quinones Sepulveda

Barry Alan Kritt

Justin Potok Bandholz

William Edward Atherton

David W Smith

Sheldon J Sigrist

Fred David Parnell

Sreekanth Konireddygari

John Joseph Carey

Alfredo Andereguia

Luis Rene Quinones Supelveda

A fan system for improved external case fan design with self-cleaning bristles, the fan system includes a housing a housing defining an opening and an interior space that extends along an axis, a plurality of fan blades positioned within the interior space and configured to rotate about the axis, and bristles positioned proximate to the opening of the housing. The fan system also includes one or more brushes configured to rotate about the axis and to be moved to a position to engage the bristles for cleaning and a mechanism configured to move the brushes to the position for engaging the bristles.

Fan systems including brushes and bristles for self-cleaning

At initiation of boot of a computing device, a processor executes a firmware interface of the computing device, like a basic input/output system (BIOS) or a unified extended firmware interface (UEFI). The processor executes the firmware interface to detect whether a dynamic hardware configuration (DHC) function has been enabled. In response to detecting that the DHC function has been enabled, the processor executes the firmware interface to configure hardware components of the computing device according to a DHC, such as to selectively disable the hardware components. After configuring the hardware components according to the DHC, the processor proceeds to boot the computing device.

Dynamic hardware configuration via firmware interface at computing device boot

A method includes running a system mainline initialization process on a compute node that includes an expansion card with read-only memory storing expansion card initialization code. The method obtains and executes the expansion card initialization code from the read-only memory to perform initialization of the expansion card. The method further includes updating a current operational progress state of the expansion card initialization stored in non-volatile memory of the node as the expansion card initialization moves through a plurality of operational progress states, detecting a fault, such as a hung condition, during the expansion card initialization in response to exceeding a predetermined time period in the current operational progress state, and storing a fault indication in the non-volatile memory, wherein the fault indication identifies the card experiencing the fault. Optionally, the method may reset the node and bypass initializing the card associated with the fault indication.

Detecting and handling an expansion card fault during system initialization

A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

Peripheral component interconnect express (PCIe) ping in a switch-based environment

Methods, apparatuses, and computer program products of extending cache in a multi-processor computer are provided. Embodiments include detecting, by a donor processor, nonuse of a donor processor's cache; broadcasting to one or more processors in the multi-processor computer, by the donor processor, a donor-ready message indicating the donor processor's cache is available for ownership transferment; receiving from a first requesting processor, by the donor processor, a first ownership-request message requesting ownership of the donor processor's cache by the first requesting processor; transmitting to the first requesting processor, by the donor processor, an ownership-grant message indicating an intention of the donor processor to transfer ownership of the donor processor's cache to the first requesting processor; and receiving from the first requesting processor, by the donor processor, an ownership-claim message indicating that the first requesting processor intends to claim ownership of the donor processor's cache.

Extending cache in a multi-processor computer

Updating a BIOS boot block security module in a plurality of compute nodes of a multinode computer including, for each compute node in the multinode computer, upon powering on the compute node: determining whether a new image of security module is available; if a new image of the security module is available, commanding the reset control module of the compute node to block an attempt by the security module to propagate a reset signal on the scalability bus to other compute nodes in the multinode computer; updating to the new image of the security module; upon completion of the update, resetting the compute node including attempting to propagate a reset signal on the scalability bus to other compute nodes in the multinode computer; and blocking the attempt to propagate the reset signal on the scalability bus.

Updating a basic input/output system ('BIOS') boot block security module in compute nodes of a multinode computer

Detection of a reset failure in a multinode data processing system is provided by a diagnostic circuit in each of a plurality of the server nodes of the system. Each diagnostic circuit is coupled to a code fetch chain of its corresponding node. At reset, prior to a node processor retrieving startup code from the code fetch chain, the diagnostic circuit provides diagnostic signals to the code fetch chain. A problem in the code fetch chain is detected from a response to the diagnostic signals. When a problem is detected, a node failure status for the problem node may be signaled to the other nodes. The multinode system may be configured in response to signaled node failure status, such as by dropping failed nodes and replacing a failed primary node with a secondary node if necessary.

Diagnosis of and response to failure at reset in a data processing system

A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data signal. The first signal line electrically couples the transmitter with the receiver. A second signal line carries a second data signal redundant to the first signal. The second signal line electrically couples the transmitter with the receiver. The receiver evaluates the first data signal to determine the presence of an error and the second node uses the second data signal if an error is detected in the first data signal.

Redundant 3-wire communication system and method

An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

Apparatus, system, and method for error assessment over a communication link

Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking mode and sending a message with error checking data to the device. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include performing an error checking operation on the message to obtain error checking data. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include retrieving the device's error checking capability from a device table.

Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol

A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (V) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

Dynamic determination of signal quality in a digital system

A redundant communication system for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data signal. The first signal line electrically couples the transmitter with the receiver. A second signal line carries a second data signal redundant to the first signal. The second signal line electrically couples the transmitter with the receiver. The receiver evaluates the first data signal to determine the presence of an error and the second node uses the second data signal if an error is detected in the first data signal.

Redundant 3-wire communication system

A jumper including a connecting face, a light-emitting face, and a light pipe extending from the connecting face to the light-emitting face is provided. The light pipe is operable to transmit a light from a provided computer hardware from the connecting face to the light-emitting face responsive to the jumper forming a circuit with the provided computer hardware. A method for fabricating a jumper is also provided. The method includes forming a plurality of receptacles on a connecting face of the jumper and incorporating a light pipe into the jumper such that the light pipe extends from the connecting face of the jumper to a light-emitting face of the jumper. A method for providing jumper installation feedback is further provided. The method includes mounting a jumper on a provided computer hardware and transmitting a light through the jumper responsive to the jumper forming a circuit with the provided computer hardware.

Growing community of inventors

Raleigh, NC, United States of America

Jeffrey Buchanan Williams