Intel Corporation

Jeffrey Baxter

Lihu Rappoport

Ahmad Yasin

Achmed Rumi Zahir

Vedaraman Geetha

Bahaa Fahim

Israel Diamand

Ibrahim Hur

Daniel W Liu

Jared W Stark

Nir Tell

Samuel D Strom

Nishant Singh

Sharada Venkateswaran

Sai Prashanth Muralidhara

Pavel Fridman

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

Code prefetch instruction

A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory

Program instructions permit software management of a processor cache. The program instructions may permit a software designer to provide software deallocation hints identifying data that is not likely to be used during further program execution. The program instructions may permit a processor to evict the identified data from a cache ahead of other eviction candidates that are likely to be used during further program execution. Thus, these software hints provide for better use of cache memory.

Optimization of cache evictions through software hints

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Los Gatos, CA, United States of America

Jeffrey Baxter