Qualcomm Incorporated

Jeffrey Baginsky Gehlhaar

Jeffrey Alexander Levin

David Jonathan Julian

Charles Wheeler Sweet, Iii

Anthony Sarah

Parag Mohan Kanade

Apparatuses and methods for detecting an obstacle in a path of an Unmanned Aerial Vehicle (UAV) are described herein, including, but not limited to, receiving data from a single image/video capturing device of the UAV, computing a score based on the received data, and performing at least one obstacle avoidance maneuver based on the score.

Unmanned aerial vehicle obstacle detection and avoidance

Certain aspects of the present disclosure support assigning neurons and/or synapses to group tags where group tags have an associated set of parameters. By using group tags, neurons or synapses in a population can be assigned a group tag. Then, by changing a parameter associated with the group tag, all synapses or neurons in the group may have that parameter changed.

Methods and apparatus for implementation of group tags for neural models

Certain aspects of the present disclosure support efficient implementation of common neuron models. In an aspect, a first memory layout can be allocated for parameters and state variables of instances of a first neuron model, and a second memory layout different from the first memory layout can be allocated for parameters and state variables of instances of a second neuron model having a different complexity than the first neuron model.

Method and apparatus for efficient implementation of common neuron models

A bus interface unit disposed for incorporation within a microprocessor system having a local microprocessor bus, a memory unit, and a system bus coupled to the memory unit is disclosed herein. The bus interface unit includes a bus control unit having an address latch for latching N-bit memory addresses impressed upon the local microprocessor bus by the microprocessor. Each of the N-bit memory addresses identifies one or more M-bit memory locations within the memory unit. The bus interface unit further includes a multiplexing interface for transferring data associated with the M-bit memory locations between the system bus and the local microprocessor bus during microprocessor memory access cycles. A programmable wait state generator serves to control the duration of the microprocessor memory access cycles in order to accommodate address and data transfer between the system bus and the local microprocessor bus during both memory read and write access cycles. In a preferred implementation the N-bit memory addresses latched during microprocessor bus cycles correspond to a sequential pair of M-bit memory locations.

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San Diego, CA, United States of America

Jeffrey Baginsky Gehlhaar