Intel Corporation

Fairchild Semiconductor Corporation

Jeffrey B Davis

Myron J Miske

Rita Chattopadhyay

Rajashri Doddamani

Byungha Joo

Xiaozhong Ji

Duc G Nguyen

Darshana Surti

Mruthunjaya Chetty

Eva Yim

Stephanie Cope

Methods, apparatus, systems, and articles of manufacture for monitoring robot health in manufacturing environments are described herein. An example system, to monitor health of a robot in a semiconductor wafer manufacturing facility, includes a sensor coupled to the robot. The sensor is to obtain a vibration signal representative of vibration of the robot. The example system also includes a health monitor extract a feature from the vibration signal, compare the feature to a threshold, and, in response to determining the feature satisfies the threshold, transmit an alert.

Methods and apparatus for monitoring robot health in manufacturing environments

Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Shallow trench avoidance in integrated circuits

Embodiments of the invention include a data buffer for connecting a core of a data circuit to a data pad. External devices may couple to the data pad even if they have a different power supply voltage than does the core of the data circuit. A pass transistor is coupled between the data pad and a data node in the buffer. A control circuit monitors a signal on the data pad and drives the pass transistor according to the signal received, thereby preventing damage due to voltage mismatch between the data circuit and the external device.

Voltage mismatch tolerant input/output buffer

An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Buffer, buffer operation and method of manufacture

An apparatus and a method for compensating the drain current degradation in pMOS transistors are disclosed. The pMOS transistor receiving drain current compensation is a primary pMOS transistor. The apparatus comprises of a plurality of pMOS transistors subject to drain current degradation correlating to drain current degradation of the primary pMOS transistor, at least one compensation pMOS transistor coupled in parallel with the primary pMOS transistor, and an output voltage decoder to activate one or more of the compensation pMOS transistors to compensate for the drain current degradation of the primary pMOS transistor based on monitored drain current degradation of the plurality of pMOS transistors.

Apparatus and a method for pMOS drain current degradation compensation

An apparatus and a method for decreasing the voltage from a source. The apparatus includes a voltage reference source. The voltage reference source is coupled to a first transistor and to a decoupling capacitor. The first transistor is a negative-channel metal oxide (&ldquo;NMOS&rdquo;) transistor which has an output voltage equal to a gate source voltage of the NMOS transistor minus an NMOS transistor threshold voltage.

Method and an apparatus for adjusting voltage from a source

A transfer gate or pass gate circuit for transferring logic signals between nodes for a range of available high-potential supply levels. The primary transfer gate is designed to protect against potentials that either exceed either a high-potential or a low-potential level or that undershoot such potential levels. For overshoot (overvoltage) tolerance, this is achieved by coupling a NMOS transistor in parallel with a pair of PMOS transistors that are coupled in series. All three transistors are located between two nodes, either of which can be the input or the output of the transfer gate. The NMOS transistor is designed to be larger than the PMOS transistors and carries most of the transfer capability. The smaller PMOS transistors are designed to eliminate potential drops that would otherwise occur with a single NMOS transistor or with a complementary pair of transistors. For undershoot (undervoltage) tolerance, a PMOS transistor is coupled in parallel with a pair of NMOS transistors that are coupled in series.

Growing community of inventors

El Dorado Hills, CA, United States of America

Jeffrey B Davis