International Business Machines Corporation

Silicon Laboratories Inc.

Jeffrey Allan Whaley

Marius Goldenberg

Michael James Mills

Yan Zhou

James Anthony Pafumi

Thomas Winters Fox

Ion Constantin Tesu

Riad S Wahby

William Alan Wall

Ashu Kohli

Mark Ernest Van Nostrand

Thomas P Lanzoni

Javier A Rodriguez

Christopher Edward Koob

One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode wherein in the inactive mode VOUT&#x2248;VSUPPLY.

Power supply with digital control loop

In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes an audio path and a pulse metering path, where the pulse metering path includes a metering generator to generate a digital sine wave from a plurality of stored values, a first interpolator to interpolate the digital sine wave, a filter to filter the interpolated digital sine wave, and a second interpolator to interpolate the filtered interpolated digital sine wave.

Method and apparatus for generating a metering pulse

In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes a cascaded digital-to-analog converter (DAC) structure including a first DAC to convert a digital sine wave into an analog representation, a second DAC to multiply the analog representation with a ramp value to obtain an unscaled output, and a third DAC to multiply the unscaled output with a gain value to generate a metering pulse.

Pulse metering architecture

A method and apparatus for optimizing processing of graphics data. An equation for use in processing graphics data is simplified by identifying variables in the equation that remain constant over a set of repeated operations. This simplified equation is implemented in a processing unit containing logic units, wherein the logic units are used to perform a graphics operation in which a set of constants is required for the graphics operation. A first set of connections is present in which these connections connect the logic units to each other, wherein the first set of connections are used to configure the plurality of logic units to determine the set of constants. A second set of connections connecting the logic units are present. This set of connections is used to configure the logic units to perform the graphics operation in which the graphics operation using the constants determined through the first set of connections.

Method and apparatus for hardware optimization of graphics pipeline functions

A method and apparatus in a data processing system for processing graphics data in a processing element. A command is received. A determination is then made as to whether the command affects processing of current graphics data within the processing element. The command is sent to a subsequent processing element if the processing element is unaffected by the command. The command is held without affecting the processing element if the command affects processing of the current graphics data within the processing element until processing of the current graphics data has completed.

Method and apparatus for attribute processing with an active pipeline stage in a data processing system

A computer system has a graphics subsystem employing a rasterizer and a frame buffer, with a digital-to-analog converter for producing drive signals to a video display. A bus interface acts as a gateway between a PCI bus and the graphics subsystem; this interface manages commands and DMAs passing between the host processor and various parts of the graphics subsystem. Within the interface, two command FIFOs are employed, one for storing commands/data sent from the host for 2D display (window management) and another for 3D applications. Using two command FIFOs eliminates the need for host semaphore, FIFO draining, and the latency associated with these operations. Timers are provided in the interface, associated with the two command FIFOs, to manage and regulate the frequency with which the system automatically switches between 2D and 3D FIFO processing. Host intervention is minimized by use of a context macro store for holding locally the sequences for context save and context restore which are used repeatedly.

Growing community of inventors

Austin, TX, United States of America

Jeffrey Allan Whaley