Advanced Micro Devices Corporation

Spansion Llc.

Adesto Technologies Corporation

Other

Globalfoundries Inc.

Advance Micro Devices, Inc.

Adesto Technologies France Sarl

Jeffrey Allan Shields

Mark T Ramsbey

Minh Van Ngo

Bharath Rangarajan

Steven C Avanzino

Khanh Q Tran

Robert C Chen

Robert Louis Dawson

Angela Tai Hui

Suzette Keefe Pangrle

Arvind Halliyal

Nicholas H Tripsas

Chakravarthy Gopalan

Ning Cheng

Tazrien Kamal

Fei Wang

Yi Ma

Allen S Yu

Jean Y Yang

Wei Ti Lee

Jusuke Ogura

Matthew S Buynoski

Sameer S Haddad

Tuan Duc Pham

Venkatesh P Gopinath

Chih-Yuh Yang

Bryan K Choo

Uzodinma Okoroanyanwu

Stephen Keetai Park

Jeff P Erhardt

Emmanuil Lingunis

Kuei-Chang Tsai

Clarence B Ferguson

Kuei Chang Tsai

Zoran Krivokapic

Calvin T Gabriel

Lu You

Minh Quoc Tran

Robert A Huertas

Guarionex Morales

Jaeyong Park

Allison Holbrook

Manuj Rathor

Igor Sokolik

James J Xie

Larry Yu Wang

Michael Vanbuskirk

Christie Marrian

John Ross Jameson

Jiahua Huang

Anne E Sanderfer

Janet Wang

Tyagamohan Gottipati

Kevin Song

Mohammad R Rakhshandehroo

Pascal Verrier

Bhanwar Singh

Ramkumar Subramanian

Paul Raymond Besser

Yu Nan Sun

Scott Allan Bell

Cyrus E Tabery

Michael Allen Van Buskirk

Hidehiko Shiraiwa

Dawn M Hopper

Yider Wu

Joong Jeon

Lewis N Shen

Alexander H Nickel

Richard Paul Kingsborough

Kouros Ghandehari

Shankar Sinha

Simon Siu-Sing Chan

Juri Krieger

Wenmei Li

Jean Yee-Mei Yang

Foroozan Sarah Koushan

John Dinh

An Chen

Mark D Kellam

Wen Yu

Connie Pin-Chin Wang

Maria Chow Chan

Joffre F Bernard

Jeffrey P Erhardt

Cinti Xiaohua Chen

Ercan Adem

Jinsong Yin

Robert J Chiu

David H Matsumoto

Ursula Q Quinto

Yi-Ching Jean Wu

Kelwin Ko

Joerg Reiss

William G Leonard

Philippe Blanchard

John Ross Jameson, Iii

Mark Russell Anderson

Russell Rosaire Austin Callahan

Jeremy Chi-Hung Chou

An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.

Memory device having programmable impedance elements with a common conductor formed below bit lines

A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.

Memory elements having conductive cap layers and methods therefor

A method can include forming a bottom structure with a top surface and a side surface that form at least one edge; forming an opening with sloped sides through at least one insulating layer to expose at least a portion of the top surface of the bottom structure; forming a programmable layer over the at least one edge, in contact with the sloped sides of the opening and the top surface of the bottom structure; and forming a top layer over the programmable layer and opening; wherein the programmable layer is programmable between at least two different impedance states.

Methods of fabricating storage elements and structures having edgeless features for programmable layer(s)

A storage element can include a bottom structure having at least one edge formed by a top surface and a side surface; a programmable layer, programmable between at least two different impedance states, and formed over the at least one edge and in contact with a portion of the bottom structure; an insulating layer that extends above the top surface of the bottom structure having an opening to the bottom structure formed therein, the opening having sloped sides; and at least one top layer formed within the opening and in contact with the programmable layer. Methods of making such a storage element are also disclosed.

Storage elements, structures and methods having edgeless features for programmable layer(s)

A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.

Memory cells with vertically integrated tunnel access device and programmable impedance element

A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.

Solid electrolyte memory elements with electrode interface for improved performance

In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.

Resistive switching devices and methods of formation thereof

A programmable memory element can include an insulating layer formed over a bottom structure; an opening formed in the insulating layer; a sidewall structure formed next to side surfaces of the opening; a tapered structure formed within the opening adjacent to the sidewall structure; and a solid electrolyte forming at least a portion of a structure selected from: the bottom structure, the sidewall structure, and the tapered structure.

Programmable memory elements, devices and methods having physically localized structure

In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.

Resistive switching devices having a buffer layer and methods of formation thereof

In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.

Resistive switching devices having alloyed electrodes and methods of formation thereof

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Damascene metal-insulator-metal (MIM) device with improved scaleability

The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Damascene metal-insulator-metal (MIM) device

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.

Ultraviolet radiation blocking interlayer dielectric

Growing community of inventors

Sunnyvale, CA, United States of America

Jeffrey Allan Shields