Mysticom Ltd.

Matsushita Electric Industrial Co., Ltd.

Tower Semiconductor Ltd.

Ceva D.s.p. Ltd.

Jeffrey Allan Jacob

Israel Greiss

Baruch Bublil

Noam Eshel

Yasuhiro Tomita

Zeev Kaplan

Hitoshi Suwa

Roni M Sadeh

Hagay Rozin

Manabu Komiya

Michael Boukaya

Dimitry Taich

Tamas Toth

Avi Parvin

Noam Dovretzki

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuitwrites a fail value to a neighbor cell bufferwhen all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer. The control circuitverifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

Flash memory and program verify method for flash memory

An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer further includes an input selector, which is coupled to toggle the input sample to at least a selected tap among the plurality of taps, responsive to a state of the equalizer, so that the equalizer operates in a first state as a feed forward equalizer, and in a second state as a blind equalizer.

Combined feed forward and blind equalizer

A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.

Filter with multipliers operating in ones complement arithmetic

Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.

Apparatus for frequency and timing recovery in a communication device

Growing community of inventors

Raanana, Israel

Jeffrey Allan Jacob