Texas Instruments Corporation

Jeffrey Alan West

Thomas Dyer Bonifield

Byron Lovell Williams

Elizabeth Costner Stewart

Margaret Simmons-Matthews

Kezhakkedath Ramunni Udayakumar

Honglin Guo

Weidong Tian

David Leonard Larkin

Basab Chatterjee

Jay Sung Chun

Eric H Warninghoff

Alan G Merriam

Zhiyi Yu

Rick A Faust

Young-Joon Park

Maxim James Franke

Paul Matthew Gillespie

Jason Chien

Mrinal Kanti Das

Arvin Nono Verdeflor

Yoshihiro Takei

Raymundo Monasterio Camenforte

Anderson Li

Mitsuhiro Sugimoto

Joseph Andre Gallegos

Robert H Havemann

Girish Anant Dixit

Qi-Zhong Hong

Manoj K Jain

Kumar Anurag Shrivastava

Masazumi Amagai

Kengo Aoya

Jeffrey E Brighton

Sreeram Subramanyam Nasum

Gregory Boyd Shinn

Hung-Yu Chou

John Britton Robbins

Eden M Zielinski

Bo-Hsun Pan

Yoshikatsu Umeda

Adrian Salinas

Sheng-Wen Huang

Steven P Zuhoski

Dhanoop Varghese

Kazuaki Mawatari

Patricia Vincent

Robert A Tuerck

Chien-Chang Li

Zi-Xian Zhan

Young Sawk Oh

Craig Beddingfield

Michael D Barth

Thomas Dyer Bonifeld

Shawn Martin O'Connor

Toshiyuki Tamura

A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiONsurface on the dielectric sidewall of the inorganic dielectric plateau. The SiONsurface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.

Stabilizing dielectric stress in a galvanic isolation device

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

Single die reinforced galvanic isolation device

An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.

Semiconductor wafer scribelane structure

An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Standalone isolation capacitor

A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Standalone high voltage galvanic isolation capacitors

A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

High voltage isolated microelectronic device

An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.

High voltage isolation barrier with electric overstress integrity

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

IC including capacitor having segmented bottom plate

An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

High performance high voltage isolators

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

Semiconductor device packages with high angle wire bonding and non-gold bond wires

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

Integrated capacitor with sidewall having reduced roughness

Growing community of inventors

Dallas, TX, United States of America

Jeffrey Alan West